Preliminary

Avance Logic, Inc.

ALC202

- 25 -

Rev0.62

http://www.realtek.com.tw

Parameter

Symbol

Min

Typ

Max

Units

BIT_CLK rise time

-

-

6

ns

BIT_CLK fall time

-

-

6

ns

SYNC rise time

-

-

6

ns

SYNC fall time

-

-

6

ns

SDATA_IN rise time

-

-

6

ns

SDATA_IN fall time

-

-

6

ns

SDATA_OUT rise time

-

-

6

ns

SDATA_OUT fall time

-

-

6

ns

Note 1: 75pF external load (50 pF in AC’97 rev2.1)

6.2.6 AC-Link Low Power Mode Timing:

Fig 6.2.6-1 AC-Link low power mode timing diagram

Parameter

Symbol

Min

Typ

Max

Units

End of slot 2 to BIT_CLK,

SDATA_IN low

-

-

1.0

us

6.2.7 ATE Test Mode:

Fig 6.2.6-1 ATE test mode timing diagram

*To meet AC’97 rev2.2, there are EAPD, SPDIFO, BIT_CLK and SDATA_IN should be floating in

test mode.

Parameter

Symbol

Min

Typ

Max

Units

Setup to trailing edge of

RESET# (also applies to SYNC)

-

-

ns

Rising edge of RESET# to Hi-Z

delay

-

-

25.0

ns