Preliminary

Avance Logic, Inc.

ALC202

- 19 -

Rev0.62

http://www.realtek.com.tw

Fig5.2-3 Default ALC202 slot arrangement – CODEC ID = 11

5.3 Reset

There are 3 kinds of reset operation. Cold, Warm and Register reset which listed below:

Reset Type

Trigger condition

CODEC response

Cold

Assert RESET# for a specified period Reset all hardware logic and all registers

to its default value.

Register

Write register indexed 00h

Reset all registers to its default value.

Warm

Driven SYNC high for specified period

without BIT_CLK

Reactivates AC-LINK, no change to

register values.

The AC97 controller should drive SYNC and SDATA-OUT low during the period of RESET# assertion to guarantee

ALC202 reset successfully.

5.4 CD Input

Pay attention to differential CD input. Below is an example of differential CD input.

Fig 5.4-1 Example of differential CD input

5.5 Odd Addressed Register Access

ALC202 will return “0000h” when those odd-addressed registers and unimplemented registers

are read.

5.6 Power-down Mode

Pay special attention to power down control register (index 26h), especially PR4 (powerdown

AC-link).

5.7 Test Mode

5.7.1 ATE In Circuit Test Mode:

SDATA_OUT is sampled high at the trailing edge of RESET#. At this mode ALC202 will drive

BIT_CLK, SDATA_IN, EAPD and SPDIFO to high impedance.

5.7.2 Vendor Specific Test Mode:

SYNC is sampled high at the trailing edge of RESET#. At this mode ALC202 will drive BIT_CLK,

SDATA_IN, EAPD and SPDIFO to high impedance.

Note: To make the most compatibility with AC’97 rev2.2, ALC202 will float its digital output pins in

both ATE and Vendor-Specific test mode. Please refer to AC’97 rev2.2 section 9.2 for detail

description about test mode.