ADF5901 datasheet(5/27 Pages) AD

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ADF5901

Data Sheet

Rev. A | Page 4 of 26

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC

Resolution

Bits

Integral Nonlinearity (INL)

±1

LSB

Differential Nonlinearity (DNL)

±1

LSB

Least Significant Bit (LSB)

7.4

REFIN CHARACTERISITICS

REFIN Input Frequency

260

MHz

−5 dBm minimum to +9 dBm maximum biased

at AHI/2 (ac coupling ensures 1.8/2 bias); for

frequencies < 10 MHz, use a dc-coupled, CMOS-

compatible square wave with a slew rate >

25 V/µs

REFIN Input Capacitance

1.2

REFIN Input Current

±100

µA

LOGIC INPUTS

Input Voltage

High (VIH)

1.4

Low (VIL)

0.6

Input Current (IINH, IINL)

±1

µA

Input Capacitance (CIN)

LOGIC OUTPUTS

Output Voltage

High (VOH)2

VDD −

0.4

Low (VOL)

0.4

Output Current

High (IOH)

500

µA

Low (IOL)

500

µA

TA = 25°C; AHI = 3.3 V; fREFIN = 100 MHz; RF = 24.125 GHz following initialization sequence in the Initialization Sequence section.

VDD selected from IO level bit (DB11 in Register 3).

TIMING SPECIFICATIONS

AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = 3.3 V ± 5%, AGND = 0 V, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise

noted. Operating temperature range is −40°C to +105°C.

Table 2. Write Timing

Parameter

Limit at TMIN to TMAX

Unit

Description

ns min

LE setup time

ns min

DATA to CLK setup time

ns min

DATA to CLK hold time

ns min

CLK high duration

ns min

CLK low duration

ns min

CLK to LE setup time

ns min

LE pulse width

ns max

LE setup time to DOUT

ns max

CLK setup time to DOUT

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