Data Sheet

ADF5901

Rev. A | Page 15 of 26

Figure 19. Register 0 (R0)

REGISTER 0

Control Bits

With Bits[C5:C1] set to 00000, Register R0 is programmed.

Figure 19 shows the input data format for programming this

register.

Auxiliary Buffer Gain

Bits[DB23:DB21] set the auxiliary output buffer gain (see

Figure 19).

Auxiliary Divide by 2

Bit DB20 selects the auxiliary output divider. Setting this bit to 0

selects divide by 2 (6 GHz output). Setting the bit to 1 selects

divide by 1 (12 GHz output).

Power-Up R Counter

Bit DB15 provides the power-up bit for the R counter block.

Setting this bit to 0 performs a power-down of the counter block.

Setting this bit to 1 returns the counter block to normal

operation.

Power-Up N Counter

Bit DB14 provides the power-up bit for the N counter block.

Setting this bit to 0 performs a power-down of the counter

block. Setting this bit to 1 returns the counter block to normal

operation.

Tx2 Amplitude Calibration

Bit DB12 provides the control bit for amplitude calibration of

the Transmitter 2 (Tx2) output. Set this bit to 0 for normal

operation. Setting this bit to 1 performs an amplitude

calibration of the Tx2 output.

Tx1 Amplitude Calibration

Bit DB11 provides the control bit for amplitude calibration of

the Tx1 output. Set this bit to 0 for normal operation. Setting

this bit to 1 performs an amplitude calibration of the Tx1

output.

Power-Up VCO

Bit DB10 provides the power-up bit for the VCO. Setting this bit

to 0 performs a power-down of the VCO. Setting this bit to 1

performs a power-up of the VCO.

VCO Calibration

Bit DB9 provides the control bit for frequency calibration of the

VCO. Set this bit to 0 for normal operation. Setting this bit to 1

performs a VCO frequency and amplitude calibration.

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4

DB3

DB2

DB1

DB0

1

0

0

0

0

0

0

0

CONTROL

BITS

AG2

AG1

AG0

AD

1

1

1

1

PRC

PNC

1

Tx2C Tx1C PVCO VCAL

PADC PTx2 PTx1 PLO

C4(0) C3(0) C2(0) C1(0)

C5(0)

RESERVED

AUX BUFFER

GAIN

PLO

0

1

PUP LO

POWER UP LO

POWER DOWN LO

PTx1

0

1

PUP Tx1

POWER UP Tx1

POWER DOWN Tx1

PTx2

0

1

PUP Tx2

POWER UP Tx2

POWER DOWN Tx2

PADC

0

1

PUP ADC

POWER UP ADC

POWER DOWN ADC

VCAL

0

1

VCO CAL

VCO FULL CAL

NORMAL OPERATION

PVCO

0

1

PUP VCO

POWER UP VCO

POWER DOWN VCO

Tx1C

0

1

Tx1 AMP CAL

Tx1 AMP CAL

NORMAL OPERATION

Tx2C

0

1

Tx2 AMP CAL

Tx2 AMP CAL

NORMAL OPERATION

AD

0

1

AUX DIV

DIV 1

DIV 2

PNC

0

1

PUP NCNTR

POWER UP NCNTR

POWER DOWN NCNTR

PNC

0

1

PUP RCNTR

POWER UP RCNTR

POWER DOWN RCNTR

AG2

AG1 AG0

AUX BUFFER GAIN

0

0

0

BUFFER DISABLED

0

0

1

GAIN SETTING 1

0

1

0

GAIN SETTING 2

0

1

1

GAIN SETTING 3

1

0

0

GAIN SETTING 4

1

0

1

GAIN SETTING 5

1

1

0

GAIN SETTING 6

1

1

1

GAIN SETTING 7

RESERVED