ADF5901

Data Sheet

Rev. A | Page 22 of 26

Figure 27. Register 8 (R8)

Figure 28. Register 9 (R9)

REGISTER 8

Control Bits

With Bits[C5:C1] set to 01000, Register R8 is programmed.

Figure 27 shows the input data format for programming this

register.

Frequency Calibration Clock

Bits[DB14:DB5] set a divider for the VCO frequency calibration

clock. Load the divider such that the time base is 10 µs (see

Figure 27).

REGISTER 9

Control Bits

With Bits[C5:C1] set to 01001, Register R9 is programmed.

Figure 28 shows the input data format for programming this

register.

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4

DB3

DB2

DB1

DB0

0

1

0

0

0

0

0

0

CONTROL

BITS

0

0

0

0

0

0

0

0

0

FC9

FC8

FC7

FC6

FC5

FC4

FC3

FC2

FC1

FC0

C4(1) C3(0) C2(0) C1(0)

FREQENCY CAL DIVIDER

C5(0)

RESERVED

FC9

FC8

...

FC4

FC3

FC2

FC1

FC0

0

0

...

0

0

0

0

0

0

0

...

0

0

0

0

1

0

0

...

0

0

0

1

0

.

.

...

.

.

.

.

.

1

2

.

.

...

.

.

.

.

.

...

1

1

...

1

1

1

0

1

1021

1

1

...

1

1

1

1

0

1023

1

1

...

1

1

1

1

1

1024

FREQUENCY CAL

DIVIDER

...

0

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4

DB3

DB2

DB1

DB0

0

0

1

0

1

0

1

0

0

CONTROL

BITS

0

1

0

0

0

0

0

1

0

1

1

1

0

0

1

0

0

1

C4(1) C3(0) C2(0) C1(1)

C5(0)

RESERVED