Data Sheet

ADF5901

Rev. A | Page 21 of 26

Figure 26. Register 7 (R7)

REGISTER 7

Control Bits

With Bits[C5:C1] set to 00111, Register R7 is programmed.

Figure 26 shows the input data format for programming

this register.

Master Reset

Bit DB25 provides a master reset bit for the device. Setting this

bit to 1 performs a reset of the device and all register maps.

Setting this bit to 0 returns the device to normal operation.

Clock Divider

Bits[DB23:DB12] set a divider for the VCO frequency calibration.

Load the divider such that the time base is 10 µs (see Figure 26).

Divide by 2 (RDIV2)

Setting the DB11 bit to 1 inserts a divide by 2 toggle flip flop

between the R counter and VCO calibration block.

Reference Doubler

R counter, disabling the doubler. Setting this bit to 1 multiplies

fed into the 5-bit R counter.

enabled is 50 MHz.

5-Bit R Divider

The 5-bit R counter allows the input reference frequency

the VCO calibration block. Division ratios from 1 to 31 are

allowed.

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2

DB1

DB0

0

0

0

0

0

0

MR

1

CONTROL

BITS

RD2

RD

R4

R3

R2

R1

R0

C4(0) C3(1) C2(1) C1(1)

C5(0)

RESERVED

R DIVIDER

R4

R3

R1

R0

R DIVIDER (R)

0

0

0

1

1

0

0

1

0

2

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1

1

0

0

28

1

1

0

1

29

1

1

1

0

30

1

1

1

1

31

RD

DOUBLER

0

DISABLED

1

ENABLED

RD2

0

DISABLED

1

ENABLED

R2

0

0

.

.

.

1

1

1

1

REF

RDIV2

MR

0

1

MASTER RESET

ENABLED

DISABLED

CLOCK DIVIDER

C1D11 C1D10

.......... C1D2 C1D0

0

0

..........

0

0

0

0

0

..........

0

1

1

0

0

..........

1

0

2

0

0

..........

1

1

3

.

.

..........

.

.

.

.

.

..........

.

.

.

.

.

..........

.

.

.

1

1

..........

0

0

4092

1

1

..........

0

1

4093

1

1

..........

1

0

4094

1

1

.........

1

1

4095

C1D11 C1D10 C1D9 C1D8 C1D7 C1D6 C1D5 C1D4 C1D3 C1D2 C1D1 C1D0

CLOCK DIVIDER