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DS2196 Datasheet(PDF) 134 Page - Dallas Semiconductor |
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DS2196 Datasheet(HTML) 134 Page - Dallas Semiconductor |
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134 / 157 page ![]() DS2196 134 of 157 12 34 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FRAME# RFSYNC RMSYNC 1 2 RFSYNC RLCLK RLINK 3 4 RLCLK RLINK 5 6 Notes: 1. RFSYNC double-wide frame sync is not enabled (RCR2.5 = 0) 2. RFSYNC double-wide frame sync is enabled (RCR2.5 = 1) 3. ZBTSI mode disabled (RCR2.6 = 0) 4. RLINKdata (FDL bits) is updated one bit time before odd frames and held for two frames 5. ZBTSI mode is enabled (RCR2.6 = 1) 6. RLINKdata (Z bits) is updated one bit time before odd frames and held for four frames Figure 21-2: RECEIVE SIDE ESF TIMING |
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