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DS2196 Datasheet(PDF) 137 Page - Dallas Semiconductor |
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DS2196 Datasheet(HTML) 137 Page - Dallas Semiconductor |
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137 / 157 page  DS2196 137 of 157 Figure 21-5: TRANSMIT SIDE ESF TIMING 12 34 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FRAME# 1 2 3 4 6 7 TSYNC TSYNC TSYNC TLCLK TLINK TLCLK TLINK Notes: 1. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is not enabled (TCR2.4 = 0) 2. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is enabled (TCR2.4 = 1) 3. TSYNC in the multiframe mode (TCR2.3 = 1) 4. ZBTSI mode disabled (TCR2.5 = 0) 5. TLINKdata (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing T1 streamif enabled via TCR1.2 6. ZBTSI mode is enabled (TCR2.5 = 1) 7. TLINKdata (Z bits) is sampled during the F-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted into the outgoing streamif enabled via TCR1.2 8. TLINKand TLCLKare not synchronous with TFSYNC |
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