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DS2196 Datasheet(PDF) 136 Page - Dallas Semiconductor |
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DS2196 Datasheet(HTML) 136 Page - Dallas Semiconductor |
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136 / 157 page ![]() DS2196 136 of 157 Figure 21-4: TRANSMIT SIDE D4 TIMING FRAME# 1 2 3 4 5 678 9 10 11 12 1 234 5 1 2 3 4 TSYNC / TFSYNC TSYNC TSYNC TLCLK TLINK Notes: 1. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is not enabled (TCR2.4 = 0) 2. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is enabled (TCR2.4 = 1) 3. TSYNC in the multiframe mode (TCR2.3 = 1) 4. TLINK data (Fs - bits) is sampled during the F-bit position of even frames for insertion into the outgoing T1 streamwhen enabled via TCR1.2 |
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