ZSSC3123AI2 datasheet(21/63 Pages) IDT

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ZSSC3123 Datasheet

January 26, 2016

2.3

Digital Core

The digital core provides control logic for the analog front-end, performs input signal conditioning, and handles external

communication. A digital signal processor (DSP) is used for conditioning and correcting the converted sensor and temperature

inputs. The DSP can correct for up to a two-region piece-wise non-linear sensor input, and up to a second order non-linear

temperature input. Alternatively a third-order correction of the sensor input for one region and up to a second-order non-linear

temperature input can be selected. Refer to section 6 for details on the signal conditioning and correction math. The analog

front-end configuration and correction coefficients for both the capacitive sensor and the temperature sensor are stored in an

on-chip EEPROM (see section 5).

Four different types of outputs are available: I

2C™, SPI, PDM, and the Alarms. These output modes are used in combination

with the two measurement modes: Update Mode and Sleep Mode. For a full description of normal operation in each mode,

refer to section 3.

The ZSSC3123 has an internal 1.85 MHz temperature-compensated oscillator that provides the time base for all operations.

When VDD exceeds the POR level, the reset signal de-asserts and the clock generator starts. See section 3.1 for the

subsequent power-up sequence. The exact clock frequency influences the measurement cycle time (see the frequency

variation spec in section 1.3). To minimize the oscillator error as the VDD voltage changes, an on-chip regulator supplies the

oscillator block.

Normal Operation Mode

Figure 3.1 gives a general overview of ZSSC3123 operation. Details of operation, including the power-up sequence,

measurement modes, output modes, diagnostics, and commands, are given in the subsequent sections.

ZSSC3123AI2 Datasheet(PDF) 21 Page - Integrated Device Technology