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ZSSC3123AI2 Datasheet(PDF) 31 Page - Integrated Device Technology

Part # ZSSC3123AI2
Description  Capacitive Sensor Signal Conditioner
PDF  63 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ZSSC3123AI2 Datasheet(HTML) 31 Page - Integrated Device Technology

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ZSSC3123 Datasheet
© 2016 Integrated Device Technology, Inc.
31
January 26, 2016
3.5
Output Modes
The ZSSC3123 has four different output modes as shown in Table 3.7. See the corresponding reference sections for specifics
on each mode.
Table 3.7
Output Modes
Output Mode
Reference Sections
I
2C
Section 3.6
Read only SPI
PDM
Section 3.7
Alarms
Section 3.8
As illustrated in the pin configuration in section 9, the output communication modes share pins. The Output_Selection bits in
EEPROM word ZMDI_Config (see section 5.1.1) select which of these outputs will be enabled. Table 3.8 shows the pin
configuration for the different output selections.
Table 3.8
Pin Assignment for Output Selections
Output Selection
I
2C™ (001
B)
SPI (011B)
PDM_C (100B)
PDM_C+T (110B)
Pin 08
Alarm_ Low
Alarm_Low
Alarm_Low
PDM_T
Pin 09
Alarm_High
Alarm_High
Alarm_High
Alarm_High
Pin 10
Ready
Ready
PDM_C
PDM_C
Pin 12
SDA
MISO
SDA
SDA
Pin 13
SCL
SCLK
SCL
SCL
Pin 14
No input
SS
No input
No Input
3.6
I
2C™ and SPI
Two wire I
2C™ and three-wire read-only SPI are available for fetching data from the ZSSC3123. I2C™ is used to send
calibration commands to ZSSC3123. To choose I
2C™ or SPI, set the corresponding Output_Selection Bits in EEPROM word
ZMDI_Config.
3.6.1
I
2C™ Features and Timing
The ZSSC3123 uses an I
2C™-compatible communication protocol‡‡ with support for 100kHz and 400kHz bit rates. The
ZSSC3123 I
2C™ slave address (00
H to 7FH) is selected by the Device_ID bits in the Cust_Config EEPROM word (see Table
5.5 for bit assignments). The device will respond only to this address if the communication lock is set by programming 011B in
the Comm_lock bits in the ZMDI_Config EEPROM word (see Table 5.2 for bit assignments); otherwise, the device will respond
to all I
2C™ addresses. The factory setting for the I2C™ slave address is 28
H with Comm_lock set.
See Figure 3.8 for the I
2C™ timing diagram and Table 3.9 for definitions of the parameters shown in the diagram.
‡‡ For details, refer to http://www.standardics.nxp.com/literature/books/i2c/pdf/i2c.bus.specification.pdf or other websites for this specification.



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