TMS320VC5421 datasheet(20/104 Pages) TI1

20 / 104 page

Introduction

December 1999 − Revised October 2008

SPRS098D

Table 2−3. Signal Descriptions (Continued)

PIN NAME

DESCRIPTION

TYPE†

DATA SIGNALS (CONTINUED)

PPD15 (MSB)

PPD14

PPD13

PPD12

PPD11

PPD10

PPD9

PPD8

PPD7

PPD6

PPD5

PPD4

PPD3

PPD2

PPD1

PPD0 (LSB)

I/O/Z¶

Parallel port data bus. The DSP uses this bidirectional data bus to access external memory when the

device is in external memory interface (EMIF) mode (the XIO pin is logic high).

This data bus is also multiplexed with the 16-bit HPI data bus. When in HPI mode, the bus is used to transfer

data between the host processor and internal DSP memory via the HPI. Refer to the HPI section of this

table for details on the secondary functions of these pins.

The data bus includes bus holders to reduce power dissipation caused by floating, unused pins. The bus

holders also eliminate the need for external pullup resistors on unused pins. When the data bus is not being

driven by the 5421, the bus holders keep data pins at the last driven logic level. The data bus keepers are

disabled at reset and can be enabled/disabled via the BH bit of the BSCR register.

These pins are placed into high-impedance state when OFF is low.

A_INT0§

B_INT0§

A_INT1§

B_INT1§

External user interrupts. A_INT0−B_INT0 are prioritized and are maskable by the interrupt mask register

(IMR) and the interrupt mode bit. A_INT1 −B_INT1 can be polled and reset by way of the interrupt flag

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

A_NMI§

B_NMI§

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR.

When NMI is activated, the processor traps to the appropriate vector location.

A_RS§

B_RS§

Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization

of the CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of

program memory. RS affects various registers and status bits.

XIO

The XIO pin is used to configure the parallel port as a host-port interface (HPI mode when XIO pin is low),

or as an asynchronous memory interface (EMIF mode when XIO pin is high).

NOTE: Because the XIO signal is asynchronous, caution must be taken when changing the state of the

XIO pin to ensure the current cycle is properly ended.

At device reset, the XIO pin level determines the initialization value of the MP/MC bit (a bit in the processor

mode status (PMST) register). Refer to the memory section for details.

† I = Input, O = Output, S = Supply, Z = High Impedance

‡ This pin has an internal pullup resistor.

§ These pins are Schmitt triggered inputs.

¶ This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

# This pin is used by Texas Instruments for device testing and should be left unconnected.

|| This pin has an internal pulldown resistor.

kAlthough this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,

a buffer is recommended to ensure the VIL and VIH specifications are met.

TMS320VC5421 Datasheet(PDF) 20 Page - Texas Instruments

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