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TMS320VC5421 Datasheet(PDF) 50 Page - Texas Instruments |
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TMS320VC5421 Datasheet(HTML) 50 Page - Texas Instruments |
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50 / 104 page  Functional Overview 50 December 1999 − Revised October 2008 SPRS098D The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in software-programmable PLL can be configured in one of two clock modes: • PLL mode. The input clock (CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved using the PLL circuitry. • DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be completely disabled in order to minimize power dissipation. The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Figure 3−20 shows the bit layout of the clock mode register and Table 3−15 describes the bit functions. 15 12 11 10 3 2 1 0 PLLMUL† PLLDIV† PLLCOUNT† PLLON/OFF† PLLNDIV STATUS R/W R/W R/W R/W R/W R/W † When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are don’t cares, and their contents are indeterminate. LEGEND: R = Read, W = Write Figure 3−20. Clock Mode Register (CLKMD) Table 3−15. Clock Mode Register (CLKMD) Bit Functions BIT NO. BIT NAME FUNCTION 15−12 PLLMUL† PLL multiplier. PLLMUL defines the frequency multiplier in conjunction with PLLDIV and PLLNDIV. See Table 3−16. PLL divider. PLLDIV defines the frequency multiplier in conjunction with PLLMUL and PLLNDIV. See Table 3−16. 11 PLLDIV† PLLDIV = 0 Means that an integer multiply factor is used 11 PLLDIV† PLLDIV = 1 Means that a noninteger multiply factor is used 10−3 PLLCOUNT† PLL counter value. PLLCOUNT specifies the number of input clock cycles (in increments of 16 cycles) for the PLL lock timer to count before the PLL begins clocking the processor after the PLL is started. The PLL counter is a down-counter, which is driven by the input clock divided by 16; therefore, for every 16 input clocks, the PLL counter decrements by one. The PLL counter can be used to ensure that the processor is not clocked until the PLL is locked, so that only valid clock signals are sent to the device. 2 PLLON/OFF† PLL on/off. PLLON/OFF enables or disables the PLL part of the clock generator in conjunction with the PLLNDIV bit (see Table 3−17). Note that PLLON/OFF and PLLNDIV can both force the PLL to run; when PLLON/OFF is high, the PLL runs independently of the state of PLLNDIV. 1 PLLNDIV PLLNDIV configures PLL mode when high or DIV mode when low. PLLNDIV defines the frequency multiplier in conjunction with PLLDIV and PLLMUL. See Table 3−16. Indicates the PLL mode. 0 STATUS STATUS = 0 Indicates DIV mode 0 STATUS STATUS = 1 Indicates PLL mode † When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are don’t cares, and their contents are indeterminate. |
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