TMS320VC5421 datasheet(25/104 Pages) TI1

25 / 104 page

Introduction

December 1999 − Revised October 2008

SPRS098D

Table 2−3. Signal Descriptions (Continued)

PIN NAME

DESCRIPTION

TYPE†

HOST-PORT INTERFACE (HPI) SIGNALS (CONTINUED)

HDS1‡§

HDS2‡§

PS‡§

DS‡§

O/Z

HPI data strobes. HDS1 and HDS2 are driven by the host read and write strobes

to control HPI transfers.

These pins are shared with the external memory interface and are only used by the

HPI when the interface is in HPI mode (XIO pin is low).

These pins are placed into the high-impedance state when OFF is low.

HR/W

R/W

O/Z

HPI read/write signal. This signal is used by the host to control the direction of an

HPI transfer.

This pin is shared with the external memory interface and is only used by the HPI

when the interface is in HPI mode (XIO pin is low).

This pin is placed into the high-impedance state when OFF is low.

HRDY

O/Z

READY

HPI data-ready output. The ready output informs the host when the HPI is ready for

the next transfer.

This pin is shared with the external memory interface and is only used by the HPI

when the interface is in HPI mode (XIO pin is low). HRDY is placed into the

high-impedance state when OFF is low.

PRIMARY

A_HINT

B_HINT

O/Z

PPA0

PPA1

O/Z

Host interrupt pin. HPI can interrupt the host by asserting this low. The host can clear

this interrupt by writing a “1” to the HINT bit of the HPIC register. Only supported in

HPI multiplexed address/data mode (HMODE pin is low). These pins are placed into

the high-impedance state when OFF is low.

HPIRS§

Host-port interface (HPI) reset pin. This signal resets the host port interface and both subsystems.

HMODE

Host mode select. When this pin is low, it selects the HPI multiplexed address/data mode. The multiplexed

address/data mode allows hosts with multiplexed address/data lines access to the HPI registers HPIC,

HPIA, and HPID. Host-to-DSP and DSP-to-host interrupts are supported in this mode.

When HMODE is high, it selects the HPI nonmultiplexed mode. HPI nonmultiplexed mode allows hosts

with separate address/data buses to access the HPI address range by way of the 18-bit address bus and

the HPI data (HPID) register via the 16-bit data bus. Host-to-DSP and DSP-to-host interrupts are not

supported in this mode.

SUPPLY PINS

AVDD

Dedicated power supply that powers the PLL. AVDD = 1.8 V. AVDD can be connected to CVDD.

CVDD

Dedicated “clean” power supply that powers the core CPUs. CVDD = 1.8 V

DVDD

Dedicated “dirty” power supply that powers the I/O pins. DVDD = 3.3 V

VSS

Digital ground. Dedicated ground plane for the device.

VSSA

Analog ground. Dedicated ground for the PLL. VSSA can be connected to VSS if digital and analog grounds

are not separated.

† I = Input, O = Output, S = Supply, Z = High Impedance

‡ This pin has an internal pullup resistor.

§ These pins are Schmitt triggered inputs.

¶ This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

# This pin is used by Texas Instruments for device testing and should be left unconnected.

|| This pin has an internal pulldown resistor.

kAlthough this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,

a buffer is recommended to ensure the VIL and VIH specifications are met.

TMS320VC5421 Datasheet(PDF) 25 Page - Texas Instruments

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