TMS320VC5421 datasheet(84/104 Pages) TI1

84 / 104 page

Electrical Specifications

December 1999 − Revised October 2008

SPRS098D

5.14.2

McBSP Transmit and Receive Timing Using CLKR/X as a Clock Source Input to

the Sample Rate Generator (SRGR)

The 5421 McBSP has been enhanced to allow the use of an external clock source as an input to the sample

rate generator (SRGR). This capability is enabled by reconfiguring either the transmit shift clock (BCLKX), or

the receive shift clock (BCLKR) to function as the input clock to the SRGR. When the McBSP is used in this

mode, the output of the SRGR is then used as a common shift clock for both the receive and transmit sections

of the serial port. This clock is output on the other of these two pins. Therefore, if BCLKX is reconfigured as

the SRGR input, then BCLKR is used as the shift clock for both the transmit and receive sections of the McBSP.

If BCLKR is reconfigured as the SRGR input, then BCLKX is used as the shift clock for both the transmit and

receive sections of the McBSP. The relevant timings for this mode of operation are depicted in Figure 5−21.

The other timings for serial port operations are the same as when using an internal clock source as described

in the standard McBSP transmit and receive timings presented in section 5.14.1.

The following timing requirements and switching characteristics tables assume testing over recommended

operating conditions and H = 0.5tc(CO) (see Figure 5−21).

Table 5−23. McBSP Sample Rate Generator Timing Requirements

MIN

MAX

UNIT

tc(BCKS)

Cycle time, SRGR clock input

tw(BCKSH)

Pulse duration, SRGR clock input high

H−4

H+1

tw(BCKSL)

Pulse duration, SRGR clock input low

H−4

H+1

tr(BCKS)

Rise time, SRGR clock input

tf(BCKS)

Fall time, SRGR clock input

Table 5−24. McBSP Sample Rate Generator Switching Characteristics

PARAMETER

MIN

MAX

UNIT

td(BCKSH-BCLKRXH) Delay time, from SRGR clock input to SRGR output

TMS320VC5421 Datasheet(PDF) 84 Page - Texas Instruments

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