TMS320VC5421 datasheet(77/104 Pages) TI1

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Electrical Specifications

December 1999 − Revised October 2008

SPRS098D

5.11 HOLD and HOLDA Timings

The following timing requirements and switching characteristics tables assume testing over recommended

operating conditions and H = 0.5tc(CO) (see Figure 5−15).

Table 5−16. HOLD and HOLDA Timing Requirements

MIN

MAX

UNIT

tw(HOLD)

Pulse duration, HOLD low

4H+10

tsu(HOLD)

Setup time, HOLD low/high before CLKOUT low

Table 5−17. HOLD and HOLDA Switching Characteristics

PARAMETER

MIN

MAX

UNIT

tdis(CLKL-A)

Disable time, address, PS, DS, IS high impedance from CLKOUT high

tdis(CLKL-RW)

Disable time, R/W high impedance from CLKOUT high

tdis(CLKL-S)

Disable time, MSTRB, IOSTRB high impedance from CLKOUT high

tdis(CLKL-D)

Disable time, Data from CLKOUT high

ten(CLKL-A)

Enable time, address, PS, DS, IS from CLKOUT high

2H+5

ten(CLKL-D)

Enable time, Data from CLKOUT high

2H+5

ten(CLKL-RW)

Enable time, R/W enabled from CLKOUT high

2H+5

ten(CLKL-S)

Enable time, MSTRB, IOSTRB enabled from CLKOUT high

2H+5

td(HOLDAL)

Delay time, HOLDA low after CLKOUT high

11H+5

td(HOLDAH)

Delay time, HOLDA high after CLKOUT high

tw(HOLDA)

Pulse duration, HOLDA low duration

2H−3

TMS320VC5421 Datasheet(PDF) 77 Page - Texas Instruments

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