TMS320VC5421 datasheet(66/104 Pages) TI1

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Electrical Specifications

December 1999 − Revised October 2008

SPRS098D

5.6

External Memory Interface Timing

5.6.1 Memory Read

External memory reads can be performed in consecutive or nonconsecutive mode under control of the

CONSEC bit in the BSCR. The following timing requirements and switching characteristics tables assume

testing over recommended operating conditions with MSTRB = 0 and H = 0.5tc(CO) (see Figure 5−4).

Table 5−7. Memory Read Timing Requirements

MIN

MAX

UNIT

ta(A)M

Access time, read data access from address valid†

2H−12

ta(MSTRBL)

Access time, read data access from MSTRB low

2H−11

tsu(D)R

Setup time, read data before CLKOUT low

th(D)R

Hold time, read data after CLKOUT low

th(A-D)R

Hold time, read data after address invalid

th(D)MSTRBH Hold time, read data after MSTRB high

† Address, PS, and DS timings are all included in timings referenced as address.

Table 5−8. Memory Read Switching Characteristics

PARAMETER

MIN

MAX

UNIT

td(CLKL-A)

Delay time, CLKOUT low to address valid†‡

−1

td(CLKH-A)

Delay time, CLKOUT high (transition) to address valid†§

−1

td(CLKL-MSL) Delay time, CLKOUT low to MSTRB low

−1

td(CLKL-MSH) Delay time, CLKOUT low to MSTRB high

− 1

th(CLKL-A)R Hold time, address valid after CLKOUT low†‡

−1

5§

th(CLKH-A)R Hold time, address valid after CLKOUT high†§

−1

6§

† Address, PS, and DS timings are all included in timings referenced as address.

‡ In the case of a memory read preceded by a memory read

§ In the case of a memory read preceded by a memory write

TMS320VC5421 Datasheet(PDF) 66 Page - Texas Instruments

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