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A8650 Datasheet(PDF) 4 Page - Allegro MicroSystems |
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A8650 Datasheet(HTML) 4 Page - Allegro MicroSystems |
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4 / 31 page ![]() Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 4 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Functional Block Diagram 125 ns Regulators ON VIN 0.8V POR Off Off S R Q Q FAULT = 1, if: EN = 0 or UVLO = 1 + - EN/SYNC VREF HICCUP = 1 if: FB < 625 mV and COMP ≈ 1.25 V and 7 OCP events EN EN/SYNC SS FB UV / OV TSD Reset Dominant Sleep OV tOFF(MIN) GND FAULT PWM_CLK CURRENT CURRENT FBOK Falling Delay Oscillator ADJ Slope ADJ Compensation Current Sense fOSC fSYNC VSSOFFS FBOK COMP CLAMP_ACTIVE CLAMP_ACTIVE VPWMOFFS POK Comparator OVP Comparator PAD + - + Error Amplifier Digital Delay POK 7 PWM Cycles 92% x VREF 88% x VREF 115% x VREF 111% x VREF 10 ns VIN 1.5 kΩ 2 kΩ POR 200 mV VIN POR VIN 20 µA PWM Comparator 10 µA OFF Clamp 1.25 V FSET 1.65 V (typ) 1.25 V (typ) 0.8 V (max) 55 mΩ Protection EN_HICCUP VIN (UVLO) EN / CLR HICCUP LATCHED HIC RST (100 mV) CURRENT (OCP) OCP COUNT EN FB HICCUP + - 350 mV 70 mΩ HICCUP EN/SYNC > 1.2 x fOSC Non-Overlap FB OFF OFF 100 kΩ SW PGND 150 nA |
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