Low Input Voltage, Adjustable Frequency

2 A Synchronous Buck Regulator with EN/SYNC and Power OK

A8650

30

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Package EJ, 10-Pin DFN

with Exposed Thermal Pad

For Reference Only – Not for Tooling Use

(Reference DWG 2860)

Dimensions in millimeters –NOT TO SCALE

Exact case and lead configuration at supplier discretion within limits shown

10

10

2

1

2

1

A

A

B

C

B

1.64

2.38

0.30

1

10

0.50

0.85

3.10

C

C

0.08

11X

C

SEATING

PLANE

D

0.25+0.05

–0.07

0.05

0.00

2.38 NOM

1.65 NOM

0.5 BSC

0.2 REF

0.75 ±0.05

3.00 ±0.15

3.00 ±0.15

0.40 ±0.10

PCB Layout Reference View

Terminal #1 mark area

Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)

Reference land pattern layout (reference IPC7351 SON50P300X300X80-11WEED3M);

all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet

application process requirements and PCB layout tolerances; when mounting on a

multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal

dissipation (reference EIA/JEDEC Standard JESD51-5)

Coplanarity includes exposed thermal pad and terminals

D