A8650 datasheet(12/31 Pages) ALLEGRO

12 / 31 page

Low Input Voltage, Adjustable Frequency

2 A Synchronous Buck Regulator with EN/SYNC and Power OK

A8650

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

not change when the synchronization function is used to alter the

switching frequency.

Sleep Mode

If the voltage at the EN/SYNC pin is low for more than 32 PWM

clock cycles, the A8650 discharges the soft start capacitor (via a

2 kΩ pulldown) until VSS ≈ 100 mV. At that time the A8650 will

enter sleep mode and draw less than IQSLEEP (3 μA (max)) from

VIN. However, the total current drawn by the VIN pin will be the

sum of the current drawn by the control circuitry plus any leakage

due to the high- and low-side MOSFETs (ILKG(HS), and ILKG(LS)).

Enable/Synchronization (EN/SYNC) Input

The enable/synchronization (EN/SYNC) input provides three

functions: enabling/disabling the A8650 with system control,

enabling/disabling the A8650 automatically, and synchronizing

the output PWM frequency synchronization to an external clock

signal input.

When EN/SYNC is being used as a system controlled enabling/

disabling logic input, when EN/SYNC is kept high, the A8650

turns on and, provided there are no fault conditions, VOUT will

ramp to its final voltage in a time set by the soft start capacitor

(CSS). When EN/SYNC is brought low for more than 32 PWM

clock cycles (see figure 2) the voltage at the soft start pin is dis-

charged by a 2 kΩ pulldown, and VSS will decay quickly starting

from the input voltage level. When VSS drops below ≈ 100 mV,

the A8650 will enter sleep mode and draw less than 3 µA from

the input. A timing diagram showing startup and shutdown using

EN/SYNC is shown in figure 8. The short delay (the 32 PWM

clock cycles between when EN/SYNC transitions to low and

when PWM switching stops) is necessary because the enable cir-

cuitry must distinguish between the relatively constant enabling/

disabling function logic levels and the longest allowed pulses

generated when the EN/SYNC frequency synchronization func-

tion also is being used.

When used in the frequency synchronization function, EN/SYNC

accepts an external clock to scale the PWM switching frequency

(fSW) from 1.2× to 1.5× above the base frequency (fOSC) set

by the RFSET resistor. The applied clock pulses must satisfy the

pulse width, duty cycle, and rise/fall time requirements shown

in the Electrical Characteristics table in this datasheet. Note that

when EN/SYNC is used as a synchronization input, soft start

still occurs at the base frequency (fOSC) and synchronization to

the external clock occurs only after soft start is complete (when

VFB > POKUV).

Finally, when used to automatically enable the A8650, the

EN/SYNC input pin is connected to VIN via a resistor, as shown

in figure 3. The series resistance is recommended to prevent large

VIN capacitors from discharging into the EN/SYNC pin at power-

down.

Power MOSFETs

The A8650 includes a 70 mΩ, high-side P-channel MOSFET

capable of delivering up to 4.1 A at 5% duty cycle. The A8650

also includes a 55 mΩ, low-side N-channel MOSFET to provide

synchronous rectification.

The low-side MOSFET continues to conduct when the induc-

tor current crosses zero to maintain constant conduction mode

(CCM). This helps to minimize EMI/EMC for noise sensitive

Figure 3. External circuit for automatically enabling the A8650 from VIN

Figure 2. PWM switching stops 32 PWM cycles after EN/SYNC transitions

low, and sleep mode begins when VSS decays to VSS_RESET (100 mV)

1 kΩ

VIN

EN/SYNC

32 PWM

cycles

Sleep mode

VSS = 100 mV

VOUT

VSS

VEN/SYNC

VCOMP

XREF

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