A8650 datasheet(14/31 Pages) ALLEGRO

14 / 31 page

Low Input Voltage, Adjustable Frequency

2 A Synchronous Buck Regulator with EN/SYNC and Power OK

A8650

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

pin increases to approximately VFB + 200 mV. At this voltage,

the error amplifier output will slew upward. Shortly thereafter,

PWM switching starts and VOUT ramps upward from the pre-

bias level. Figure 5 shows startup when the output voltage is

pre-biased to 0.9 V.

Power OK (POK) Output

The Power OK (POK) output is an open drain output, so an exter-

nal pull-up resistor must be connected to it. An internal compara-

tor monitors the voltage at the FB pin and controls the internal

open drain N-MOSFET at the POK pin. POK is high when the

voltage at the FB pin is within regulation. The POK output is

pulled low if any of the following are true:

• VFB is rising, and is < 92% of the internal reference voltage, or

• VFB is rising, and is > 115% of the internal reference voltage, or

• EN/SYNC is low for more than 32 PWM clock cycles, or

• VIN pin UVLO occurs, or

• Thermal Shutdown (TSD) occurs.

If the A8650 is running and EN/SYNC transitions low for

more than 32 PWM clock cycles, then POK will transition low

and remain low only as long as the internal circuitry is able to

enhance the open-drain output device. When VIN fully collapses,

POK will return to the high impedance state. The POK compara-

tor incorporates hysteresis to prevent chattering due to voltage

ripple at the FB pin.

Protection Features

Undervoltage Lockout (UVLO)

An undervoltage lockout (UVLO) comparator monitors the volt-

age at the VIN pin and keeps the regulator disabled if the voltage

is below the lockout threshold (VINUVSTART). The UVLO com-

parator incorporates enough hysteresis (VINUVHYS) to prevent

on/off cycling of the regulator due to IR drops in the VIN path

during heavy loading or during startup. Figure 8 shows the A8650

operation for a UVLO-initiated startup (EN/SYNC = high, VIN

ramps up).

Thermal Shutdown (TSD)

The A8650 protects itself from overheating by means of an

internal thermal monitoring circuit. If the junction temperature

exceeds the thermal shutdown threshold (TTSD, 170°C (typ)) the

voltages at the soft start and COMP pins will be pulled to GND

and both the high-side and low-side MOSFETs will be turned

off. The A8650 will automatically restart when the junction

temperature decreases more than the thermal shutdown hysteresis

(TTSDHYS, 20°C(typ)). Figure 8 shows the A8650 operation dur-

ing and after a TSD event.

Overvoltage Protection (OVP)

The A8650 uses the FB pin to provide a basic level of overvolt-

age protection. An overvoltage condition could occur if the load

current decreases very quickly or the regulator output is pulled

high by some external voltage. When an overvoltage condition

is detected, POK is pulled low and PWM switching stops. The

COMP and soft start pins are not directly affected by OVP. If the

regulator output decreases back to the allowed operating range,

POK will transition to high and PWM switching will resume.

Cycle-by-Cycle Overcurrent Protection (OCP)

The A8650 monitors the current in the high-side MOSFET and

if the current exceeds the cycle-by-cycle overcurrent threshold

(ILIM) then the high-side MOSFET is turned off. Normal PWM

operation resumes on the next clock pulse from the oscillator. The

A8650 includes leading edge blanking to prevent falsely trigger-

ing the cycle-by-cycle current limit when the upper MOSFET is

turned on.

Because of the addition of the slope compensation ramp to the

inductor current, the A8650 delivers more current at lower duty

cycles and less current at higher duty cycles. For a given duty

cycle, this results in a little more current being available at lower

switching frequencies than at higher frequencies.

Figure 5. Startup to VOUT = 1.8 V, VOUT pre-biased to 0.9 V

VSS

VEN/SYNC

VCOMP

VOUT

VSS =

200 mV

Switching starts when

VCOMP > 350 mV

COMP pin released at

VSS > VFB + 200 mV

VOUT rises

from 0.9 V

VOUT = 1.8 V

VOUT = 0.9 V

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