A8650 datasheet(13/31 Pages) ALLEGRO

13 / 31 page

Low Input Voltage, Adjustable Frequency

2 A Synchronous Buck Regulator with EN/SYNC and Power OK

A8650

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

applications by eliminating the SW output high-frequency ringing

associated with discontinuous conduction mode (DCM). When a

fault occurs or the A8650 is disabled, the SW pin becomes high

impedance by turning off both the upper and lower MOSFETs.

Pulse Width Modulation (PWM)

A high-speed PWM comparator, capable of pulse widths less

than 105 ns, is included in the A8650. The inverting input of

the comparator is connected to the output of the error amplifier.

The non-inverting input is connected to the sum of the current

sense signal, the slope compensation, and the PWM Ramp Offset

(VPWMOFFS).

At the beginning of each PWM cycle, the PWM_CLK signal

sets the PWM flip flop and the high-side MOSFET is turned

on. When the summation of the current sense signal, the slope

compensation, and the DC PWM Ramp Offset rises above the

error amplifier voltage, the comparator resets the PWM flip flop

and the high-side MOSFET is turned off. After a short delay to

prevent cross-conduction (tNO), the low-side MOSFET is turned

on. The PWM flip flop is reset dominant so, if the output volt-

age of the error amplifier drops below the PWM Ramp Offset,

then PWM 0% duty cycle (that is, pulse skipping) operation is

achieved.

Current Sense Amplifier

A high-bandwidth current sense amplifier monitors the current

in the high-side MOSFET. The current signal is supplied to the

PWM comparator, the cycle-by-cycle current limiter, and the hic-

cup mode counter.

Soft Start (Startup) and Inrush Current Control

Inrush currents to the regulator are controlled by the soft start

function. When the A8650 is enabled, after all faults are cleared

the soft start pin will source approximately 20 μA ( ISSSU) and

the voltage on the soft start capacitor (CSS) will ramp upward

from 0 V. When the voltage at the soft start pin exceeds the Soft

Start Offset (VSSOFFS, 200 mV(typ)), the error amplifier output

slews upward and, shortly thereafter, PWM switching will begin.

As shown in figure 4, there is a short delay (tSS(DELAY)) between

when the EN/SYNC pin transitions high and when the soft start

voltage reaches 200 mV.

After the A8650 starts switching, the error amplifier will regu-

late the voltage at the FB pin to the soft start pin voltage minus

the Soft Start Offset voltage. After switching starts, the voltage

at the SS pin will rise from 200 mV to 1000 mV, a difference of

800 mV. At the same time, the voltage at the FB pin will rise from

0 V to 800 mV and the regulator output voltage will rise from 0 V

to the setpoint determined by the feedback resistor divider (RFB1

and RFB2).

When the voltage at the soft start pin reaches approximately

1000 mV, the error amplifier will change mode and begin regulat-

ing to the A8650 internal reference, 800 mV. The voltage at the

soft start pin will continue to rise to approximately VIN. Com-

plete soft start operation is shown in figure 4.

During startup, the PWM switching frequency is scaled linearly

from fOSC / 3 to fOSC as the voltage at the FB pin ramps from 0 V

to 600 mV. This is done to prevent the output inductor current

from climbing to a level that may damage the A8650 when the

input voltage is high and the output of the regulator is either

shorted or soft starting a relatively high capacitance or very

heavy load.

Pre-Biased Startup

If the output capacitors are pre-biased, the A8650 will shift the

startup routine parameters to prevent discharging the output

capacitors. Normally, PWM switching starts when the voltage at

the soft start pin reaches approximately 200 mV. However, in the

case with pre-biasing, the voltage at the FB pin (VFB) is non-

zero. Switching will not start until the voltage at the soft-start

VSS

VEN/SYNC

tSS(DELAY)

tSS

VCOMP

VOUT

VSS = 200 mV

VSS = 1000 mV

Switching starts when

VCOMP > 350 mV

VOUT = 1.8 V

Figure 4. Startup to VOUT = 1.8 V, at IOUT = 2.0 A with CSS = 10 nF

A8650 Datasheet(PDF) 13 Page - Allegro MicroSystems

A8650 Datasheet(HTML) 13 Page - Allegro MicroSystems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL