A8650 datasheet(25/31 Pages) ALLEGRO

25 / 31 page

Low Input Voltage, Adjustable Frequency

2 A Synchronous Buck Regulator with EN/SYNC and Power OK

A8650

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

5. Calculate the frequency of the ESR zero (fZ1) formed by the

output capacitor(s). Use equation 23 (repeated here):

fZ1

COUT

ESR

2�

If fZ1 is at least one decade higher than the target crossover

frequency (fC) then fZ1 can be ignored. This is usually the case

for a design using ceramic output capacitors. Use equation 27 to

calculate the value of CP by setting fP3 to either 5 × fC or fSW / 2,

whichever is higher.

Alternatively, if fZ1 is near or below the target crossover fre-

quency (fC), then use equation 27 to calculate the value of CP by

setting fP3 equal to fZ1. This is usually the case for a design using

high ESR electrolytic output capacitors.

Power Dissipation and Thermal Calculations

The power dissipated in the A8650 is the sum of the power dis-

sipated from the VIN supply current (PIN), the power dissipated

due to the switching of the internal power high-side MOSFET

(PSW1), the power dissipated due to the rms current being

conducted by the high- and low-side MOSFETs (PCOND1 and

PCOND2), the power dissipated by the low-side MOSFET body

diode during the non-overlap times, and the power dissipated by

the internal gate drivers (PDRIVER1 and PDRIVER2).

The power dissipated from the VIN supply current can be calcu-

lated using the following equation:

PIN = VIN × IQ + (VIN – VGS) × (QG1 + QG2 ) × fSW

(30)

where

VIN is the input voltage,

IQ is the input quiescent current drawn by the A8650 (nominally

2 mA),

VGS is the MOSFET gate drive voltage, typically 5.0 V,

QG1 and QG2 are the internal high- and low-side MOSFET gate

charges (approximately 3.3 nC and 1.4 nC respectively), and

fSW is the PWM switching frequency.

The switching losses dissipated by the internal high-side

MOSFET during PWM switching can be calculated using the

following equation:

PSW1

VIN IOUT

fSW

(tr + tf )

(31)

where

VIN is the input voltage,

IOUT is the output current,

fSW is the PWM switching frequency, and

tr and tf are the rise and fall times measured at the SW node.

Approximate values for tr range from 10 to 15 ns. The fall time

is usually about 50% faster than the rise time.

The conduction losses dissipated by the high-side MOSFET

while it is conducting can be calculated using the

following equation:

PCOND1 Irms(FET) RDS(on)HS

VOUT

VIN

+ 12

∆IL2

IOUT

RDS(on)HS

(32)

where

IOUT is the regulator output current,

ΔIL is the peak-to-peak inductor ripple current, and

RDS(on)HS is the on-resistance of the high-side MOSFET.

The conduction losses dissipated by the low-side MOSFET while

it is conducting can be calculated using the following equation:

PCOND2 Irms(FET) RDS(on)LS

VOUT

VIN

–

∆IL2

IOUT

RDS(on)LS

(33)

where

IOUT is the regulator output current,

ΔIL is the peak-to-peak inductor ripple current, and

RDS(on)LS is the on-resistance of the low-side MOSFET.

The RDS(on)of the MOSFETs has some initial tolerance plus an

increase from self-heating and elevated ambient temperatures.

A conservative design should accommodate an RDS(on) with

at least a 15% initial tolerance plus 0.39%/°C increase due to

temperature.

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