A8650 datasheet(22/31 Pages) ALLEGRO

22 / 31 page

Low Input Voltage, Adjustable Frequency

2 A Synchronous Buck Regulator with EN/SYNC and Power OK

A8650

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

is higher than the cycle-by-cycle current threshold, as shown in

figure 12. This phenomena is more pronounced when using high

value electrolytic type output capacitors. To avoid prematurely

triggering hiccup mode the soft start capacitor, CSS, should be

calculated according to:

≥

CSS

COUT

VOUT

ISSSU

0.8 (V)

ICO

(18)

where VOUT is the output voltage, COUT is the output capacitance,

ICO is the amount of current allowed to charge the output capaci-

tance during soft start (recommend 0.1 A < ICO < 0.3 A). Higher

values of ICO result in faster soft start times. However, lower

values of ICO ensure that hiccup mode is not falsely triggered.

Allegro recommends starting the design with an ICO of 0.1 A and

increasing it only if the soft start time is too slow. If a non-stan-

dard capacitor value for CSS is calculated, the next larger value

should be used.

The output voltage ramp time, tSS, can be calculated by using

either of the following methods:

tSS

COUT

CSS

ISSSU

VOUT

0.8 (V)

ICO

(19)

(20)

When the A8650 is in hiccup mode, the soft start capacitor is

used as a timing capacitor and sets the hiccup period. The soft

start pin charges the soft start capacitor with ISSSU during a

startup attempt, and discharges the same capacitor with ISSHIC

between startup attempts. Because the ratio ISSSU / ISSHIC is

approximately 2:1, the time between hiccups will be about two

times as long as the startup time. Therefore, the effective duty-

cycle of the A8650 will be very low and the junction temperature

will be kept low.

Compensation Components (RZ, CZ, CP)

To compensate the system it is important to understand where

the buck power stage, load resistance, and output capacitance

form their poles and zeros in frequency. Also, its important to

understand not only that the (Type II) compensated error ampli-

fier introduces a zero and two more poles, but also where these

should be placed to maximize system stability, provide a high

bandwidth, and optimize the transient response.

First, consider the power stage of the A8650, the output capaci-

tors, and the load resistance. This circuitry is commonly referred

as the control-to-output (CO) transfer function. The low fre-

quency gain of this circuitry depends on the COMP to SW current

gain (gmPOWER), and the value of the load resistor (RL). The DC

gain (GCO(0HZ)) of the control-to-output is:

GCO(0Hz) = gmPOWER × RL

(21)

The control-to-output transfer function has a pole (fP1), formed

by the output capacitance (COUT) and load resistance (RL),

located at:

fP1

COUT

2�

(22)

The control-to-output transfer function also has a zero (fZ1)

formed by the output capacitance (COUT) and its associated ESR:

fZ1

COUT

ESR

2�

(23)

For a design with very low-ESR type output capacitors (such as

ceramic capacitors), the ESR zero (fZ1) is usually at a very high

frequency, so it can be ignored. On the other hand, if the ESR

zero falls below or near the 0 dB crossover frequency of the

system (as is the case with electrolytic output capacitors), then it

should be cancelled by the pole formed by the CP capacitor and

the RZ resistor (discussed and identified later as fP3).

A Bode plot of the control-to-output transfer function for the

A8650 circuit shown in the typical application schematic on the

front page (VOUT = 1.8 V, IOUT = 2.0 A, RL = 0.9 Ω) is shown in

figure 13. The pole at fP1 can easily be seen at 8.8 kHz while the

ESR zero, fZ1, occurs at a very high frequency, 4 MHz (this is

Figure 12. Output current (ICO) during startup

Output

capacitor

current, ICO

}

ILIM

ILOAD

tSS

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