TS8388BCGL datasheet(13/57 Pages) ATMEL

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TS8388B

2144C–BDC–04/03

Package

Description

Pin Description

Note:

1. The common mode level of the output buffers is 1.2V below the positive digital supply.

For ECL compatibility the positive digital supply must be set at 0V (ground).

For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.

If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the posi-

tive digital supply level in the same proportion in order to spare power dissipation.

Table 7. TS8388BGL Pin Description (CBGA68 package)

Symbol

Pin number

Function

GND

A2, A5, B1, B5, B10, C2, D2, E1, E2, E11,

F1, F2, G11, K2, K3, K4, K5, K10, L2, L5

Ground pins.

To be connected to external ground plane.

VCC

A4, A6, B2, B4, B6, H1, H2, L6, L7

+5V positive supply.

A3, B3, G1, G2, J1, J2

5V analog negative supply.

DVEE

F10, F11

-5V digital negative supply.

VIN

In phase (+) analog input signal of the Sample and Hold

differential preamplifier.

VINB

Inverted phase (-) of ECL clock input signal (CLK).

CLK

In phase (+) ECL clock input signal. The analog input is

sampled and held on the rising edge of the CLK signal.

CLKB

Inverted phase (-) of ECL clock input signal (CLK).

B0, B1, B2, B3, B4,

B5, B6, B7

A8, A9, A10, D10, H11, J11, K9, K8

In phase (+) digital outputs.

B0 is the LSB. B7 is the MSB.

B0B, B1B, B2B, B3B,

B4B, B5B, B6B, B7B

B7, B8, B9, C11, G10, H10, L10, L9

Inverted phase (-) digital outputs.

B0B is the inverted LSB. B7B is the inverted MSB.

In phase (+) Out of Range Bit. Out of Range is high on the

leading edge of code 0 and code 256.

ORB

Inverted phase (+) Out of Range Bit (OR).

E10

In phase (+) output of Data Ready Signal.

DRB

D11

Inverted phase (-) output of Data Ready Signal (DR).

GORB

Gray or Binary select output format control pin.

- Binary output format if GORB is floating or V

CC.

- Gray output format if GORB is connected at ground (0V).

GAIN

ADC gain adjust pin. The gain pin is by default grounded, the

ADC gain transfer fuction is nominally close to one.

DIOD/DRRB

Die function temperature measurement pin and

asynchronous data ready reset active low, single-ended ECL

input.

VPLUSD

B11, C10, J10, K11

+2.4V for LVDS output levels otherwise to GND(2).

A1, A11, L1, L11

Not connected.

TS8388BCGL Datasheet(PDF) 13 Page - ATMEL Corporation

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