TS8388BCGL datasheet(31/57 Pages) ATMEL

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TS8388B

2144C–BDC–04/03

No performance degradation (i.e.: due to timing jitter) is observed in this particular single-

ended configuration up to 1.2 GSPS Nyquist conditions (F

IN = 600 MHz).

This is true so long as the inverted phase clock input pin is 50

Ω terminated very closely to one

of the neighboring shield ground pins, which constitutes the local Ground reference for the

inphase clock input.

Thus the TS8388B differential clock input buffer will fully reject the local ground noise (and any

capacitively and inductively coupled noise) as common mode effects. Moreover, a very low

phase noise sinewave generator must be used for enhanced jitter performance.

The typical inphase clock input amplitude is 1V peak to peak, centered on 0V (ground) com-

mon mode. This corresponds to a typical clock input power level of 4 dBm into the 50

Ω

termination resistor. Do not exceed 10 dBm to avoid saturation of the preamplifier input

transistors.

The inverted phase clock input is grounded through the 50

Ω termination resistor.

Figure 31. Single-ended Clock Input (Ground common mode):

VCLK Common Mode = 0V; VCLKB = 0V; 4 dBm Typical Clock Input Power Level (into 50

Ω termination resistor)

Note:

Do not exceed 10 dBm into the 50

Ω termination resistor for single clock input power level.

Differential ECL Clock

Input

The clock inputs can be driven differentially with nominal -0.8V/-1.8V ECL levels.

In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, fol-

lowed by a power splitter (hybrid junction) in order to obtain 180 degrees out of phase

sinewave signals. Biasing tees can be used for offseting the common mode voltage to ECL

levels.

Note: As the biasing tees propagation times are not matching, a tunable delay line is required

in order to ensure the signals to be 180 degrees out of phase especially at fast clock rates in

the GSPS range.

Figure 32. Differential Clock Inputs (ECL Levels)

Ω

(external or

on package)

1 M

Ω

0.4 pF

-0.5V

+0.5V

[V]

VCLK

CLK or CLKB double pad (pins 37, 38 or 39, 40)

CLK or CLKB

Ω reverse termination

VCLK = 0V

VCLK

Ω

(external or

on package)

1 M

Ω

0.4 pF

CLK or CLKB double pad (pins 37, 38 or 39, 40)

CLK or CLKB

-2V

Ω reverse termination

-1.8V

-0.8V

[mV]

VCLK

VCLKB

Common mode = -1.3V

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