TS8388BCGL datasheet(6/57 Pages) ATMEL

6 / 57 page

TS8388B

2144C–BDC–04/03

Digital Outputs

Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,

Tj (typical) = 70

°C.

(1)(6)

Logic compatibility for digital outputs

(Depending on the value of VPLUSD)

(See Application Notes)

–

ECL or LVDS

–

Differential output voltage swings

(assuming VPLUSD = 0V):

–

–––

–

Ω open transmission lines (ECL levels)

–

1.5

1.620

–

Ω differentially terminated

–

0.70

0.825

–

Ω differentially terminated

–

0.54

0.660

–

Output levels (assuming VPLUSD = 0V)

Ω open transmission lines:

–

–––

–

(6)

Logic “0” voltage

VOL

–

-1.62

-1.54

Logic “1” voltage

–-0.88

-0.8

–

Output levels (assuming VPLUSD = 0V)

Ω differentially terminated:

–

–––

–

(6)

Logic “0” voltage

VOL

–

-1.41

-1.34

Logic “1” voltage

–-1.07

-1

–

Output levels (assuming V

PLUSD = 0V)

Ω differentially terminated:

–

–––

–

(6)

Logic “0” voltage

1, 2

–

-1.40

-1.32

-1.25

Logic “1” voltage

1, 2

-1.16

-1.25

-1.10

–

Differential Output Swing

DOS

270

300

–

Output level drift with temperature

–

1.6

mV/

°C

DC Accuracy (CBGA68 package)

Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format

Tj (typical) = 70

°C.

Differential non linearity

DNL-

-0.6

-0.4

–

lsb

(2)(3)

Differential non linearity

DNL+

–

0.4

0.6

lsb

Integral non linearity

INL-

-1.2

-0.7

–

lsb

(2)(3)

Integral non linearity

INL+

–

0.7

1.2

lsb

No missing codes

–

Guaranteed over specified temperature range

(3)

Gain

–

1, 2

110

Input offset voltage

–

1, 2

-26

-5

Table 3. Electrical Specifications (Continued)

Parameter

Symbol

Test

Level

Value

Unit

Note

Min

Typ

Max

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