TS8388BCGL datasheet(33/57 Pages) ATMEL

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TS8388B

2144C–BDC–04/03

Three possible line driving and back-termination scenarios are proposed (assuming V

PLUSD =

0V):

Ω impedance transmission lines, 75Ω differentially terminated (Figure 34):

Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading

to ±0.41V = 0.825V in differential, around -1.21V (respectively +1.21V) common mode for

PLUSD = 0V (respectively 2.4V).

Ω impedance transmission lines, 50Ω differentially termination (Figure 35):

Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V),

leading to ±0.33V = 660 mV in differential, around -1.18V (respectively +1.21V) common

mode for V

PLUSD = 0V (respectively 2.4V).

Ω impedance open transmission lines (Figure 36):

Each output voltage varies between -1.6V and -0.8V (respectively +0.8V and +1.6V),

which are true ECL levels, leading to ±0.8V = 1.6V in differential, around -1.2V (respec-

tively +1.2V) common mode for V

PLUSD = 0V (respectively 2.4V). Therefore, it is possible

to drive directly high input impedance storing registers, without terminating the 75

Ω trans-

mission lines. In time domain, that means that the incident wave will reflect at the 75

Ω

transmission line output and travel back to the generator (i.e.: the 75

Ω data output buffer).

As the buffer output impedance is 75

Ω, no back reflection will occur.

Note: This is no longer true if a 50

Ω transmission line is used, as the latter is not matching the

buffer 75

Ω output impedance.

Each differential output termination length must be kept identical. It is recommended to decou-

ple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode

perturbation in case of slight mismatch in the differential output line lengths.

Too large mismatches (keep < a few mm) in the differential line lengths will lead to switching

currents flowing into the decoupling capacitor leading to switching ground noise.

The differential output voltage levels (75

Ω or 50Ω termination) are not ECL standard voltage

levels, however it is possible to drive standard logic ECL circuitry like the ECLinPS logic line

from Motorola®.

At sampling rates exceeding 1 GSPS, it may be difficult to trigger any Acquisition System with

digital outputs. It becomes necessary to regenerate digital data and Data Ready by means of

external amplifiers, in order to be able to test the TS8388B at its optimum performance

conditions.

TS8388BCGL Datasheet(PDF) 33 Page - ATMEL Corporation

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