TS8388BCGL datasheet(32/57 Pages) ATMEL

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TS8388B

2144C–BDC–04/03

Single-ended ECL

Clock Input

In single-ended configuration enter on CLK (resp. CLKB) pin, with the inverted phase Clock

input pin CLKB (respectively CLK) connected to -1.3V through the 50

Ω termination resistor.

The inphase input amplitude is 1V peak to peak, centered on -1.3V common mode.

Figure 33. Single-ended Clocl Input (ECL):

VCLK Common Mode = -1.3V; VCLKB = -1.3V

Noise Immunity

Information

Circuit noise immunity performance begins at design level.

Efforts have been made on the design in order to make the device as insensitive as possible

to chip environment perturbations resulting from the circuit itself or induced by external cir-

cuitry (Cascode stages isolation, internal damping resistors, clamps, internal (on-chip)

decoupling capacitors).

Furthermore, the fully differential operation from analog input up to the digital outputs provides

enhanced noise immunity by common mode noise rejection.

Common mode noise voltage induced on the differential analog and clock inputs will be can-

celed out by these balanced differential amplifiers.

Moreover, proper active signals shielding has been provided on the chip to reduce the amount

of coupled noise on the active inputs.

The analog inputs and clock inputs of the TS8388B device have been surrounded by ground

pins, which must be directly connected to the external ground plane.

Digital Outputs

The TS8388B differential output buffers are internally 75

Ω loaded. The 75Ω resistors are con-

nected to the digital ground pins through a -0.8V level shift diode (see Figure 34, Figure 35,

Figure 36 on page 35).

The TS8388B output buffers are designed for driving 75

Ω (default) or 50Ω properly terminated

impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of the

Ω resistors when switching ensures a 0.825V voltage drop across the resistor (untermi-

nated outputs).

The V

PLUSD positive supply voltage allows the adjustment of the output common mode level

from -1.2V (V

PLUSD = 0V for ECL output compatibility) to +1.2V (VPLUSD = 2.4V for LVDS output

compatibility).

Therefore, the single-ended output voltages vary approximately between -0.8V and -1.625V,

(outputs unterminated), around -1.2V common mode voltage.

-1.8V

-0.8V

[V]

VCLK

VCLKB = -1.3V

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