| Electronic Components Datasheet Search |
|
S7G2 Datasheet(PDF) 46 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
S7G2 Datasheet(HTML) 46 Page - Renesas Technology Corp |
|
46 / 116 page ![]() R01DS0262EU0100 Rev.1.00 Page 46 of 113 Feb 23, 2016 S7G2 2. Electrical Characteristics 2.3.3 Reset Timing Figure 2.8 Power-on reset timing Figure 2.9 Reset input timing Table 2.15 Reset timing Item Symbol Min Typ Max Unit Test conditions RES pulse width Power-on LDO mode tRESWP 1- - ms Figure 2.8 DCDC mode 1.5 - - ms Deep Software Standby mode tRESWD 0.6 - - ms Figure 2.9 Software Standby mode, Subosc-speed mode tRESWS 0.3 - - ms All other tRESW 200 - - μs Wait time after RES cancellation tRESWT - - 33.4 μs Figure 2.8 Wait time after internal reset cancellation (IWDT reset, WDT reset, software reset, SRAM parity error reset, SRAM ECC error reset, bus master MPU error reset, bus slave MPU error reset, stack pointer error reset) tRESW2 - - 390 μs- VCC RES Internal reset signal (low is valid) tRESWP tRESWT RES Internal reset signal (low is valid) tRESWD, tRESWS, tRESW tRESWT |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |