S7G2 datasheet(80/116 Pages) RENESAS

80 / 116 page

R01DS0262EU0100 Rev.1.00

Page 80 of 113

Feb 23, 2016

S7G2

2. Electrical Characteristics

Figure 2.55

SSI data transmit and receive timing when SSICR.SCKP = 1

Figure 2.56

SSI data output delay after SSIWSn change

2.3.15

SD/MMC Host Interface Timing

Table 2.30

SD/MMC Host Interface signal timing

Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register.

Clock duty ratio is 50%.

Item

Symbol

Min

Max

Unit

Test conditions

SDCLK clock cycle

TSDCYC

Figure 2.57

SDCLK clock high pulse width

TSDWH

6.5

SDCLK clock low pulse width

TSDWL

6.5

SDCLK clock rise time

TSDLH

-3

SDCLK clock fall time

TSDHL

-3

SDCMD/SDDAT output data delay

TSDODLY

–6

SDCMD/SDDAT input data setup

TSDIS

SDCMD/SDDAT input data hold

TSDIH

tSR

tHTR

tDTR

SSISCKn

(Input or Output)

SSIWSn, SSIDATAn

(Input)

SSIWSn, SSIDATAn

(Output)

tDTRW

SSIWSn (input)

SSIDATAn (output)

MSB bit output delay after SSIWSn change for Slave

transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0]=DWL[2:0]

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