S7G2 datasheet(85/116 Pages) RENESAS

85 / 116 page

R01DS0262EU0100 Rev.1.00

Page 85 of 113

Feb 23, 2016

S7G2

2. Electrical Characteristics

2.3.17

PDC Timing

Note 1. tPBcyc: PCLKB cycle.

Figure 2.68

PDC input clock timing

Figure 2.69

PDC output clock timing

Table 2.32

PDC timing

Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

Item

Symbol

Min

Max

Unit

Test

conditions

PDC

PIXCLK input cycle time

tPIXcyc

Figure 2.68

PIXCLK input high pulse width

tPIXH

PIXCLK input low pulse width

tPIXL

PIXCLK rise time

tPIXr

-5

PIXCLK fall time

tPIXf

-5

PCKO output cycle time

tPCKcyc

2 × tPBcyc

-ns

Figure 2.69

PCKO output high pulse width

tPCKH

(tPCKcyc – tPCKr – tPCKf)/2 – 3

PCKO output low pulse width

tPCKL

(tPCKcyc – tPCKr – tPCKf)/2 – 3

PCKO rise time

tPCKr

-5

PCKO fall time

tPCKf

-5

VSYNV/HSYNC input setup time

tSYNCS

Figure 2.70

VSYNV/HSYNC input hold time

tSYNCH

PIXD input setup time

tPIXDS

PIXD input hold time

tPIXDH

tPIXcyc

tPIXH

tPIXf

tPIXL

tPIXr

PIXCLK input

tPCKcyc

tPCKH

tPCKf

tPCKL

tPCKr

PCKO pin output

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