S7G2 datasheet(3/116 Pages) RENESAS

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R01DS0262EU0100 Rev.1.00

Page 3 of 113

Feb 23, 2016

S7G2

1. Overview

Resets

14 resets:

 RES pin reset

 Power-on reset

 Voltage monitor reset 0

 Voltage monitor reset 1

 Voltage monitor reset 2

 Independent Watchdog Timer reset

 Watchdog Timer reset

 Deep Software Standby reset

 SRAM parity error reset

 SRAM DED error reset

 Bus master MPU error reset

 Bus slave MPU error reset

 Stack pointer error reset

 Software reset.

See section 6, Resets in User's Manual.

Low Voltage Detection (LVD)

The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and

the detection level can be selected in the software program. See section 8, Low Voltage

Detection (LVD) in User's Manual.

Clocks

 Main clock oscillator (MOSC)

 Sub-clock oscillator (SOSC)

 High-speed on-chip oscillator (HOCO)

 Middle-speed on-chip oscillator (MOCO)

 Low-speed on-chip oscillator (LOCO)

 PLL frequency synthesizer

 Independent Watchdog Timer (WDT) on-chip oscillator

 Clock out supports.

See section 9, Clock Generation Circuit in User's Manual.

Clock Frequency Accuracy

Measurement Circuit (CAC)

The CAC checks the system clock frequency with a reference clock signal by counting the

number of pulses of the system clock to be measured. The reference clock can be provided

externally through a CACREF pin or internally from various on-chip oscillators.

Event signals can be generated when the clock does not match or measurement ends. This

feature is particularly useful in implementing a fail-safe mechanism for home and industrial

automation applications.

See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User's Manual.

Low-power modes

Power consumption can be reduced in multiple ways, including by setting clock dividers,

controlling EBCLK output, controlling SDCLK output, stopping modules, selecting power

control mode in normal operation, and transitioning to low-power modes. See section 11, Low-

Power Modes in User's Manual.

Battery backup function

A battery backup function is provided for partial powering by a battery. The battery-powered

area includes the RTC, SOSC, backup memory, and switch between VCC and VBATT. See

section 12, Battery Backup Function in User's Manual.

The register write protection function protects important registers from being overwritten

because of software errors. See section 13, Register Write Protection in User's Manual.

Memory Protection Unit (MPU)

Two MPUs and a CPU stack pointer monitor functions are provided for memory protection.

See section 16, Memory Protection Unit (MPU) in User's Manual.

Watchdog Timer (WDT)

The WDT is a 14-bit down-counter. It can be used to reset the MCU when the counter

underflows because the system has run out of control and is unable to refresh the WDT. In

addition, a non-maskable interrupt or interrupt can be generated by an underflow.

A refresh-permitted period can be set to refresh the counter and be used as the condition for

detecting when the system runs out of control. See section 27, Watchdog Timer (WDT) in

User's Manual.

Independent Watchdog Timer (IWDT)

The IWDT consists of a 14-bit down-counter that must be serviced periodically to prevent

counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-

maskable interrupt or interrupt for a timer underflow. Because the timer operates with an

independent, dedicated clock source, it is particularly useful in returning the MCU to a known

state as a fail safe mechanism when the system runs out of control. The IWDT can be

triggered automatically on a reset, underflow, or refresh error, or by a refresh of the count value

in the registers. See section 28, Independent Watchdog Timer (IWDT) in User's Manual.

Table 1.3

System (2/2)

Feature

Functional description

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