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DM505 Datasheet(PDF) 117 Page - Texas Instruments

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Part # DM505
Description  SoC for Vision Analytics 15mm Package (ABF) Silicon Revision 2.0
PDF  290 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DM505 Datasheet(HTML) 117 Page - Texas Instruments

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DM505
www.ti.com
SPRS976D – NOVEMBER 2016 – REVISED JULY 2017
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Specifications
Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-32. Camera Parallel Interface (CPI) IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
cpi_data2
G18
1
G18
1
cpi_data3
G21
1
G21
1
cpi_data4
G22
1
G22
1
cpi_data5
H18
1
H18
1
cpi_data6
H20
1
H20
1
cpi_data7
H19
1
H19
1
cpi_data8
H22
1
H22
1
cpi_data9
H21
1
H21
1
cpi_data10
J17
1
J17
1
cpi_data11
K22
1
K22
1
cpi_data12
K21
1
K21
1
cpi_data13
K18
1
K18
1
cpi_data14
K17
1
K17
1
cpi_data15
L21
1
cpi_wen
K19
1
K19
1
cpi_fid
K20
1
K20
1
cpi_hsync
F21
1
F21
1
cpi_vsync
F20
1
F20
1
cam_nreset
W6
1
cam_strobe
B18
3
M17
1
cam_shutter
C18
3
M18
1
For more information, please contact your local TI representative.
5.9.6.5
EMIF
The device has a dedicated interface to DDR3 and DDR3L SDRAM. It supports JEDEC standard
compliant DDR3 and DDR3L SDRAM devices with the following features:
•
16-bit or 32-bit data path to external SDRAM memory
•
Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices (Single die only)
•
One interface with associated DDR3/DDR3L PHYs
NOTE
For more information, see the EMIF Controller section of the Device TRM.
5.9.6.6
GPMC
The GPMC is the unified memory controller that interfaces external memory devices such as:
•
Asynchronous SRAM-like memories and ASIC devices
•
Asynchronous page mode and synchronous burst NOR flash
•
NAND flash
NOTE
For more information, see the General-Purpose Memory Controller section of the Device
TRM.



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