Texas Instruments Incorporated

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GC1012B 3.3V DIGITAL TUNER

SLWS138B

This document contains information which may be changed at any time without notice

Figure 2. Filter Response

1.7

GAIN

The programmable bandwidth filter is followed by a gain circuit which adjusts the output level in 0.03

dB steps. The gain is controlled by the power of two gain value S and the fractional gain value F. The input

255, and B is the base gain setting for each value of D. The base gain setting B gives a unity input to output

gain for the chip, i.e., a 12 bit constant going into the chip will come out in the 12 MSBs of the 16 bit output

word. The values of B are:

D

B

16

25

44

83

16

2

32

1

64

0

The S and F gain settings are double buffered so that they can be applied synchronously. A new

gain setting takes effect either when S is loaded, or, if the GS_MODE control bit is used, when the GS strobe

is received.

The gain settings and GS_MODE bit are stored in control registers 6 and 7.

Overflow detection circuitry detects overflow conditions in the gain output words and saturates the

samples to plus or minus full scale. Overflows are reported in the STATUS register and on the OFLOW

output pin. The overflow status can be used to detect if the gain settings are too high.

(a) Overall

(b) Passband