Texas Instruments Incorporated

- 23 -

GC1012B 3.3V DIGITAL TUNER

SLWS138B

This document contains information which may be changed at any time without notice

5.7

EXAMPLE RECEIVER ARCHITECTURE

An example digital receiver architecture using the GC1012B chip is shown in Figure 7.

Figure 7. Example Digital Receiver Architecture

The receiver contains an analog front end which downconverts up to 30MHz of radio spectrum to

analog to digital converter (ADC). The ADC digitizes the signal using up to 12 bits of resolution at a sampling

rate up to 60 MHZ. The GC1012B chip tunes, downconverts, and narrowband filters desired frequencies

from within the 30 MHz band. The GC1012B output can either be converted back to analog or kept in its

digital state for subsequent signal processing.

1. Note that the HF spectrum (1 to 30MHz) can be digitized directly.

ANALOG

FRONT

END

ANALOG

TO

DIGITAL

GC1012B

CHIP

CONVERTER

•

GAIN

•

BANDLIMIT

TO

30MHz OR LESS

•

DOWNCONVERT

•

OUTPUT IS

CENTERED AROUND

15MHz

•

DIGITIZES TO 8, 10

OR 12 BITS

•

60 MHz SAMPLING

RATE

•

TUNES TO

DESIRED

FREQUENCY

•

NARROWBAND

FILTERS SIGNAL

•

REDUCES

SAMPLE RATE

•

CONVERTS BACK TO

ANALOG

SIGNAL

OUT

FROM

ANTENNAE

USER

INTERFACE

DIGITAL

TO

ANALOG

CONVERTER

(OPTIONAL)