Texas Instruments Incorporated

- 9 -

GC1012B 3.3V DIGITAL TUNER

SLWS138B

This document contains information which may be changed at any time without notice

SIGNAL

DESCRIPTION

X[0:11]

INPUT DATA. Active high

The 12 bit two’s complement input samples. New samples are clocked into the chip on the rising edge of the clock. The input

data rate is assumed to be equal to the clock rate.

CK

CLOCK INPUT. Active high

The clock input to the chip. The X, SS, GS and AS signals are clocked into the chip on the rising edge of this clock. The I,

Q, WS, IFLAG, OS, OFLOW and SO signals are clocked out on the rising edge of this clock.

SS

SYSTEM SYNC. Active low

The sync input to the chip. All timers, accumulators, and control counters are, or can be, synchronized to SS. Bits in control

register 4 (see Section 3.2) determine the operation of SS. This sync is clocked into the chip on the rising edge of the clock.

AS

ACCUMULATOR SYNC. Active low

The accumulator sync is provided to synchronously change tuning frequencies. This sync can be used to load a new tuning

frequency into the frequency register and/or to clear the frequency accumulator. This signal is clocked into the chip on the

rising edge of the clock.

GS

GAIN SYNC. Active low

The gain sync is provided to synchronously change gain settings. This signal is clocked into the chip on the rising edge of

the clock.

I[0:15]

IN-PHASE OUTPUT DATA. Active high

The I part of each complex output sample is output as a 16 bit word on this pin. The bits are clocked out on the rising edge

of the clock.

OEI

IN-PHASE OUTPUT ENABLE. Active low

The I[0:15] output pins are put into a high impedance state when this pin is high.

Q[0:15]

QUADRATURE OUTPUT DATA. Active high

The Q part of each complex output sample is output as a 16 bit word on this pin. The bits are clocked out on the rising edge

of the clock.

OEQ

QUADRATURE OUTPUT ENABLE. Active low

The Q[0:15] output pins are put into a high impedance state when this pin is high.

WS

WORD STROBE. Programmable active high or low level

This strobe is output synchronous with the I and Q data words. The strobe occurs once per bit and is either one clock wide

or has a 50% duty cycle. The high/low polarity of the strobe is programmable. See Section 3.5 for details.

IFLAG

IN-PHASE STROBE. Active high

This strobe identifies the in-phase half of a complex pair when the outputs are in the IQ_MUX mode. See Section 3.5 for

details. This signal is high when the I-half is output and is low when the Q-half is output.

SO

SYNC OUT. Active low

This signal is either a delayed version of the input system sync SS, or, if SS_MUX in control register 4 is set, is the internally

INT

INTERRUPT OUT. Active low

This signal is the READY flag from control register 9. This interrupt goes active when a new output sample is ready in control

registers 12, 13, 14, and 15.

OS

ONE SHOT STROBE. Active low

This output is a one-shot sync strobe generated by writing to control address 10. The strobe is one clock cycle wide.

OFLOW

OVERFLOW FLAG. Active low

This signal goes low when an overflow is detected in the gain circuit. The signal will either pulse low for one clock cycle or

will stay low depending upon the state of the OFLOW_MODE bit in control register 9.

C[0:7]

CONTROL DATA I/O BUS. Active high

This is the 8 bit control data I/O bus. Control register data is loaded into the chip or read from the chip through these pins.

The chip will only drive these pins when CS is low and R/W is high.

A[0:3]

CONTROL ADDRESS BUS. Active high

These pins are used to address the 16 control registers within the chip. Each of the 16 control registers within the chip are

assigned a unique address. A control register can be written to or read from by setting A[0:3] to the register’s address.

RE

READ STROBE. Active low

The RE strobe is used to read the control registers. Control register data is output when both RE and CE are low.

WE

WRITE STROBE. Active low

The WE strobe is used to write the control registers. Control register data is written when both WE and CE are low.

CE

CHIP ENABLE. Active low

This control enables the read or write operation. The contents of the register selected by A[0:3] will be output on C[0:7]

when RE is low and CE is low. If WE is low when CE goes low, then the selected register will be loaded with the contents

of C[0:7].