Texas Instruments Incorporated

- 14 -

GC1012B 3.3V DIGITAL TUNER

SLWS138B

This document contains information which may be changed at any time without notice

3.4

GAIN CONTROL REGISTERS

These registers set the output gain.

ADDRESS 6:

Gain Control Register

BIT

TYPE

NAME

DESCRIPTION

0-7

R/WF[0:7] The 8 bit gain fraction.

ADDRESS 7:

Gain Exponent Register

BIT

TYPE

NAME

DESCRIPTION

0-3

R/W

S[0:3]

The 4 bit gain exponent.

4

R/W

GS_MODE

Turns on the synchronous gain mode. See below.

5

R/W

CKDET_DISABLE

Provided for testability. Turns off the clock loss detect function in the powerdown

circuit. This bit powers up low and should be kept low.

6

R

-

unused

7

R

-

unused.

The chip’s input to output gain is set using F and S according to the formula:

where B is the base gain setting which is a function of the decimation mode of the chip. The unity gain

setting (S=B and F=0) means that a 12 bit DC input will show up in the upper 12 bits of the 16 bit output.

The values of B are:

DEC

B

0 or 1

6

25

34

43

52

61

70

The GS_MODE control bit determines when new gain settings are applied to the output. New gain

settings are double buffered so that they can be synchronized with the output words. If GS_MODE is low,

then the gain settings are applied to the output samples immediately after S has been loaded. If GS_MODE

is high, then the new gain settings are not used until GS goes low.

NOTE: The gain settings must be loaded in the correct order- F first and then S. The circuit detects

new gain settings by sensing when S is loaded. this means that S must be loaded even if one only wishes

to change F.