AD4020 datasheet(36/37 Pages) AD

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Data Sheet

AD4020

Rev. A | Page 35 of 36

LAYOUT GUIDELINES

The PCB that houses the AD4020 must be designed so that the

analog and digital sections are separated and confined to certain

areas of the board. The pinout of the AD4020, with its analog

signals on the left side and its digital signals on the right side,

eases this task.

Avoid running digital lines under the device because they couple

noise onto the die, unless a ground plane under the AD4020 is

used as a shield. Fast switching signals, such as CNV or clocks,

must not run near analog signal paths. Avoid crossover of

digital and analog signals.

At least one ground plane must be used. It can be common or

split between the digital and analog sections. In the latter case,

join the planes underneath the AD4020 devices.

The AD4020 voltage reference input (REF) has a dynamic

input impedance. Decouple the REF pin with minimal parasitic

inductances by placing the reference decoupling ceramic capacitor

close to (ideally right up against) the REF and GND pins, and

connect them with wide, low impedance traces.

Finally, decouple the VDD and VIO power supplies of the AD4020

with ceramic capacitors, typically 100 nF, placed close to the

AD4020 and connected using short, wide traces to provide low

impedance paths and to reduce the effect of glitches on the

power supply lines.

An example of a layout following these rules is shown in

Figure 65 and Figure 66.

EVALUATING THE AD4020 PERFORMANCE

Other recommended layouts for the AD4020 are outlined in the

user guide of the evaluation board for the AD4020 (EVAL-

AD4020FMCZ). The evaluation board package includes a fully

assembled and tested evaluation board, user guide, and software

for controlling the board from a PC via the EVAL-SDP-CH1Z.

Figure

65. Example Layout of the AD4020 (Top Layer)

Figure

66. Example Layout of the AD4020 (Bottom Layer)

AD4020 Datasheet(PDF) 36 Page - Analog Devices