AD4020 datasheet(26/37 Pages) AD

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Data Sheet

AD4020

Rev. A | Page 25 of 36

Status bits can also be clocked out at the end of the conversion

data if the status bits are enabled in the configuration register.

There are six status bits in total as described in Table 12.

The AD4020 is configured by 16-bit SPI writes to the desired

configuration register. The 16-bit word can be written via the

SDI line while CNV is held low. The 16-bit word consists of an

8-bit header and 8-bit register data. For isolated systems, the

ADuM141D is recommended, which has a maximum clock rate

of 75 MHz and allows the AD4020 to run at 1.8 MSPS.

The AD4020 register bits are programmable and their default

statuses are shown in Table 12. The register map is shown in

Table 14. The overvoltage clamp flag is a read only sticky bit,

and it is cleared only if the register is read and the overvoltage

condition is no longer present. It gives an indication of

overvoltage condition when it is set to 0.

Table 12. Register Bits

Default Status

Overvoltage (OV) Clamp Flag

1 bit (default 1: inactive)

Turbo Mode

1 bit (default 0: disabled)

High-Z Mode

1 bit (default 0: disabled)

Span Compression

1 bit (default 0: disabled)

Enable Six Status Bits

1 bit (default 0: disabled)

All access to the register map must start with a write to the 8-bit

command register in the SPI interface block. The AD4020 ignores

all 1s until the first 0 is clocked in; the value loaded into the

command register is always a 0 followed by seven command bits.

This command determines whether that operation is a write or

a read. The AD4020 command register is shown in Table 13.

Table 13. Command Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WEN

R/W

All register read/writes must occur while CNV is low. Data on

SDI is clocked in on the rising edge of SCK. Data on SDO is

clocked out on the falling edge of SCK. At the end of the data

transfer, SDO is put in a high impedance state on the rising

edge of CNV if daisy-chain mode is not enabled. If daisy-chain

mode is enabled, SDO goes low on the rising edge of CNV. Register

reads are not allowed in daisy-chain mode.

During register write, to read the current conversion results on

SDO, the CNV pin must be brought low after the conversion is

completed; otherwise, the conversion results may be incorrect

on SDO; however, the register write occurs regardless.

The LSB of each configuration register is reserved because a

user reading 16-bit conversion data may be limited to a 16-bit

SPI frame. The state of SDI on the last bit in the SDI frame may

be the state that then persists as CNV rises. Because the state of

SDI when CNV rises is part of how the user sets the interface

mode, the user in this scenario may need to set the final SDI

state on that basis.

The timing diagrams in Figure 47 through Figure 49 show how

data is read and written when the AD4020 is configured in

Table 14. Register Map

ADDR[1:0]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x0

Reserved

Enable six

status bits

Span

compression

High-Z

mode

Turbo

mode

Overvoltage (OV) clamp

flag (read only sticky bit)

0xE1

tCYC

tSCK

tDIS

tSCKL

tSCKH

tSCNVSCK

tSSDISCK

tHSDISCK

tCNVH

tEN

CNV

SCK

WEN

R/W

ADDR[1:0]

SDI

SDO

tHSDO

tDSDO

D19

D18

D17

D16

D15

D14

D13

D12

Figure 47. Register Read Timing Diagram

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