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AD4020

Data Sheet

Rev. A | Page 22 of 36

Multiplexed Applications

The AD4020 significantly reduces system complexity and cost

for multiplexed applications that require superior performance

in terms of noise, power, and throughput. Figure 39 shows a

simplified block diagram of a multiplexed data acquisition

system including a multiplexer, an ADC driver, and the

precision SAR ADC.

SAR ADC

ADC

DRIVER

MULTIPLEXER

Figure 39. Multiplexed Data Acquisition Signal Chain Using the AD4020

Switching multiplexer channels typically results in large voltage

steps at the ADC inputs. To ensure an accurate conversion result,

the step must be given adequate time to settle before the ADC

samples its inputs (on the rising edge of CNV). The settling

time error is dependent on the drive circuitry (multiplexer and

ADC driver), RC filter values, and the time when the multiplexer

channels are switched. Switch the multiplexer channels

immediately after tQUIET1 has elapsed from the start of the

conversion to maximize settling time while preventing

corruption of the conversion result. To avoid conversion

corruption, do not switch the channels during the tQUIET1 time.

If the analog inputs are multiplexed during the quiet conversion

time (tQUIET1), the current conversion may be corrupted.

EASE OF DRIVE FEATURES

Input Span Compression

In single-supply applications, it is desirable to use the full range

of the ADC; however, the amplifier can have some headroom

and footroom requirements, which can be a problem, even if it

is a rail-to-rail input and output amplifier. The use of span

compression increases the headroom and footroom available to

the amplifier by reducing the input range by 10% from the top and

bottom of the range while still accessing all available ADC codes

(see Figure 40). The SNR decreases by approximately 1.9 dB (20 ×

log(8/10)) for the reduced input range when span compression is

enabled. Span compression is disabled by default but can be

enabled by writing to the relevant register bit (see the Digital

Interface section).

ADC

VREF = 4.096V

DIGITAL OUTPUT

ALL 2N

CODES

+FSR

–FSR

90% OF VREF = 3.69V

10% OF VREF = 0.41V

ANALOG

INPUT

IN+

Figure 40. Span Compression

High-Z Mode

The AD4020 incorporates high-Z mode, which reduces the

nonlinear charge kickback when the capacitor DAC switches

back to the input at the start of acquisition. Figure 41 shows the

input current of the AD4020 with high-Z mode enabled and

disabled. The low input current makes the ADC easier to drive

than the traditional SAR ADCs available in the market, even

with high-Z mode disabled. The input current reduces further

to submicroampere range when high-Z mode is enabled. The

high-Z mode is disabled by default, but it can be enabled by

writing to the register (see Table 14). Disable high-Z mode for

input frequencies above 100 kHz or multiplexing.

–12

–6

–9

–3

–15

–5

–1

–3

–2

–4

INPUT DIFFERENTIAL VOLTAGE (V)

25°C HIGH-Z ENABLED

25°C HIGH-Z DISABLED

Figure 41. Input Current vs. Input Differential Voltage,

VIO = 3.3 V, VREF = 5 V

System designers looking to achieve the optimum data sheet

performance from high resolution precision SAR ADCs are often

forced to use a dedicated high power, high speed amplifier to

drive the traditional switched capacitor SAR ADC inputs for

their precision applications, which is one of the common pain

points encountered in designing a precision data acquisition

signal chain. The benefits of high-Z mode are low input current

for slow (<10 kHz) or dc type signals and improved distortion

(THD) performance over a frequency up to 100 kHz. High-Z

mode allows a choice of lower power and bandwidth precision

amplifiers with a lower RC filter cutoff to drive the ADC, removing

the need for dedicated high speed ADC drivers, which saves system

power, size, and cost in precision, low bandwidth applications.

High-Z mode allows the amplifier and RC filter in front of the

ADC to be chosen based on the signal bandwidth of interest

and not based on the settling requirements of the switched

capacitor SAR ADC inputs.

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