Data Sheet

AD4020

Rev. A | Page 27 of 36

STATUS WORD

The 6-bit status word can be appended to the end of a

conversion result, and the default conditions of these bits are

defined in Table 15. The status bits must be enabled in the

register setting. When the overvoltage clamp flag is a 0, it

indicates an overvoltage condition. The overvoltage clamp flag

status bit updates on a per conversion basis.

The SDO line goes to high-Z after the sixth status bit is clocked

out (except in daisy-chain mode). The user is not required to

clock out all status bits to start the next conversion. The serial

interface timing for CS mode, 3-wire without busy indicator,

including status bits, is shown in Figure 50.

Table 15. Status Bits (Default Conditions)

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Overvoltage (OV) clamp flag

Span compression

High-Z mode

Turbo mode

Reserved

Reserved

SDO

D19

D18

D17

D1

D0

SCK

1

2

3

18

19

20

CNV

CONVERSION

ACQUISITION

ACQUISITION

SDI = 1

25

26

STATUS BITS B[5:0]

B1

B0

24

Figure 50. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram Including Status Bits (SDI High)