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AD4020

Data Sheet

Rev. A | Page 30 of 36

CS MODE, 3-WIRE WITH THE BUSY INDICATOR

This mode is typically used when a single AD4020 is connected

to an SPI-compatible digital host with an interrupt input (IRQ).

The connection diagram is shown in Figure 55, and the

corresponding timing diagram is shown in Figure 56.

With SDI tied to VIO, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. SDO

is maintained in high impedance until the completion of the

conversion irrespective of the state of CNV. Prior to the minimum

conversion time, CNV can select other SPI devices, such as analog

multiplexers; however, CNV must be returned low before the

minimum conversion time elapses and then held low for the

maximum possible conversion time to guarantee the generation

of the busy signal indicator.

When the conversion is complete, SDO goes from high impedance

to low impedance. With a pull-up resistor of 1 kΩ on the SDO

line, this transition can be used as an interrupt signal to initiate

the data reading controlled by the digital host. The AD4020

then enters the acquisition phase and powers down. The data

bits are then clocked out, MSB first, by subsequent SCK falling

edges. The data is valid on both SCK edges. Although the rising

edge can capture the data, a digital host using the SCK falling

edge allows a faster reading rate, provided it has an acceptable

hold time. After the optional 21st SCK falling edge or when

CNV goes high (whichever occurs first), SDO returns to high

impedance.

If multiple AD4020 devices are selected at the same time, the

SDO output pin handles this contention without damage or

induced latch-up. Meanwhile, it is recommended to keep this

contention as short as possible to limit extra power dissipation.

There must not be any digital activity on the SCK during the

conversion.

SDI

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

VIO

IRQ

VIO

1kΩ

AD4020

Figure 55. CS Mode, 3-Wire with the Busy Indicator Connection Diagram (SDI High)

SDO

D19

D18

tDIS

SCK

tSCK

tSCKL

tSCKH

tHSDO

tDSDO

CNV

CONVERSION

ACQUISITION

tCONV

tCYC

ACQUISITION

SDI = 1

tCNVH

tACQ

tQUIET2

Figure 56. CS Mode, 3-Wire with the Busy Indicator Serial Interface Timing Diagram (SDI High)

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