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AD4020

Data Sheet

Rev. A | Page 24 of 36

to consider the optimum size of capacitance necessary to keep

the reference buffer stable as well as to meet the minimum ADC

requirement stated previously in this section.

POWER SUPPLY

The AD4020 uses two power supply pins: a core supply (VDD) and

a digital input/output interface supply (VIO). VIO allows direct

interface with any logic between 1.8 V and 5.5 V. To reduce the

number of supplies needed, VIO and VDD can be tied together

for 1.8 V operation. The ADP7118 low noise, CMOS, low

dropout (LDO) linear regulator is recommended to power the

VDD and VIO pins. The AD4020 is independent of power supply

sequencing between VIO and VDD. Additionally, the AD4020 is

insensitive to power supply variations over a wide frequency

range, as shown in Figure 45.

100

10k

100k

FREQUENCY (Hz)

Figure 45. PSRR vs. Frequency, VIO = 3.3 V, VREF = 5 V

The AD4020 powers down automatically at the end of each

conversion phase; therefore, the power scales linearly with the

sampling rate. This feature makes the device ideal for low

sampling rates (even of a few hertz) and battery-powered

applications. Figure 46 shows the AD4020 total power

dissipation and individual power dissipation for each rail.

0.01

0.10

100

10k

100k

100

10k

100k

1M 1.8M

THROUGHPUT (SPS)

VDD

VIO

VREF

TOTAL POWER

Figure 46. Power Dissipation vs. Throughput, VIO = 1.8 V, VREF = 5 V

DIGITAL INTERFACE

Although the AD4020 has a reduced number of pins, it offers

flexibility in its serial interface modes. The AD4020 can also be

programmed via 16-bit SPI writes to the configuration registers.

When in CS mode, the AD4020 is compatible with SPI, QSPI™,

digital hosts, and DSPs. In this mode, the AD4020 can use either

a 3-wire or 4-wire interface. A 3-wire interface using the CNV,

SCK, and SDO signals minimizes wiring connections, which is

useful, for instance, in isolated applications. A 4-wire interface

using the SDI, CNV, SCK, and SDO signals allows CNV, which

initiates the conversions, to be independent of the readback

timing (SDI). This interface is useful in low jitter sampling or

simultaneous sampling applications.

The AD4020 provides a daisy-chain feature using the SDI input

for cascading multiple ADCs on a single data line similar to a

shift register.

The mode in which the device operates depends on the SDI

level when the CNV rising edge occurs. CS mode is selected if

SDI is high, and daisy-chain mode is selected if SDI is low. The

SDI hold time is such that when SDI and CNV are connected

together, daisy-chain mode is always selected.

In either 3-wire or 4-wire mode, the AD4020 offers the option of

forcing a start bit in front of the data bits. This start bit can be

used as a busy signal indicator to interrupt the digital host and

trigger the data reading. Otherwise, without a busy indicator, the

user must time out the maximum conversion time prior to

readback.

The busy indicator feature is enabled in CS mode if CNV or SDI

is low when the ADC conversion ends.

The SDO state upon power-up is high-Z for a few milliseconds

and it changes to either low or high-Z depending on the states of

CNV and SDI, as shown in in Table 11.

Table 11. State of SDO Upon Power-Up

CNV

SDI

SDO

Low

High-Z

The AD4020 has a turbo mode capability in both 3-wire and 4-wire

mode. Turbo mode is enabled by writing to the configuration

Turbo mode allows a slower SPI clock rate, making interfacing

simpler. A throughput rate of 1.8 MSPS can be achieved only

with turbo mode enabled and a minimum SCK rate of 71 MHz.

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