AD4020 datasheet(20/37 Pages) AD

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Data Sheet

AD4020

Rev. A | Page 19 of 36

ANALOG INPUTS

Figure 34 shows an equivalent circuit of the analog input

structure, including the overvoltage clamp of the AD4020.

CEXT

REXT

VIN

REF

IN+/IN–

GND

CLAMP

0V TO 15V

RIN

CIN

CPIN

Figure 34. Equivalent Analog Input Circuit

Input Overvoltage Clamp Circuit

Most ADC analog inputs, IN+ and IN−, have no overvoltage

protection circuitry apart from ESD protection diodes. During

an overvoltage event, an ESD protection diode from an analog

input (IN+ or IN−) pin to REF forward biases and shorts the

input pin to REF, potentially overloading the reference or causing

damage to the device. The AD4020 internal overvoltage clamp

circuit with a larger external resistor (REXT = 200 Ω) eliminates

the need for external protection diodes and protects the ADC

inputs against dc overvoltages.

In applications where the amplifier rails are greater than VREF

and less than ground, it is possible for the output to exceed the

input voltage range of the device. In this case, the AD4020

internal voltage clamp circuit ensures that the voltage on the

input pin does not exceed VREF + 0.4 V and prevents damage to

the device by clamping the input voltage in a safe operating range

and avoiding disturbance of the reference; this feature is particu-

larly important for systems that share the reference among

multiple ADCs.

If the analog input exceeds the reference voltage by 0.4 V, the

internal clamp circuit turns on and the current flows through

the clamp into ground, preventing the input from rising further

and potentially causing damage to the device. The clamp turns

on before D1 (see Figure 34) and can sink up to 50 mA of current.

When active, the clamp sets the overvoltage (OV) clamp flag bit

in the register that can be read back (see Table 14), which is a

sticky bit that must be read to be cleared. The status of the clamp

can also be checked in the status bits using an overvoltage (OV)

clamp flag (see Table 15). The clamp circuit does not dissipate

static power in the off state. Note that the clamp cannot sustain

the overvoltage condition for an indefinite amount of time.

The external RC filter is usually present at the ADC input to band

limit the input signal. During an overvoltage event, excessive

voltage is dropped across REXT, and REXT becomes part of a

protection circuit. The REXT value can vary from 200 Ω to 20 kΩ

for 15 V protection. The CEXT value can be as low as 100 pF for

correct operation of the clamp. See Table 1 for input overvoltage

clamp specifications.

Differential Input Considerations

The analog input structure allows the sampling of the true

differential signal between IN+ and IN−. By using these differential

inputs, signals common to both inputs are rejected. Figure 35

shows the common-mode rejection capability of the AD4020

over frequency. It is important to note that the differential input

signals must be truly antiphase in nature, 180° out of phase, which

is required to keep the common-mode voltage of the input signal

within the specified range around VREF/2, as shown in Table 1.

100

10k

100k

FREQUENCY (Hz)

Figure 35. Common-Mode Rejection Ratio (CMRR) vs. Frequency, VIO = 3.3 V,

VREF = 5 V, TA = 25°C

Switched Capacitor Input

During the acquisition phase, the impedance of the analog

inputs (IN+ or IN−) can be modeled as a parallel combination

of Capacitor CPIN and the network formed by the series connection

of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically

400 Ω and is a lumped component composed of serial resistors

and the on resistance of the switches. CIN is typically 40 pF and

is mainly the ADC sampling capacitor.

During the conversion phase, where the switches are open, the

input impedance is limited to CPIN. RIN and CIN make a single-

pole, low-pass filter that reduces undesirable aliasing effects and

limits noise.

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