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AD4020

Data Sheet

Rev. A | Page 28 of 36

CS MODE, 3-WIRE TURBO MODE

This mode is typically used when a single AD4020 is connected

to an SPI-compatible digital host. It provides additional time

during the end of the ADC conversion process to clock out the

previous conversion result, providing a lower SCK rate. The

AD4020 can achieve a throughput rate of 1.8 MSPS only when

turbo mode is enabled and using a minimum SCK rate of

71 MHz. The connection diagram is shown in Figure 51,

and the corresponding timing diagram is shown in Figure 52.

This mode replaces the 3-wire with busy indicator mode by

programming the turbo mode bit, Bit 1 (see Table 14).

When SDI is forced high, a rising edge on CNV initiates a

conversion. The previous conversion data is available to read

after the CNV rising edge. The user must wait tQUIET1 time after

CNV is brought high before bringing CNV low to clock out the

previous conversion result. The user must also wait tQUIET2 time

after the last falling edge of SCK to when CNV is brought high.

When the conversion is complete, the AD4020 enters the

acquisition phase and powers down. When CNV goes low, the

MSB is output to SDO. The remaining data bits are clocked by

subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can capture the data, a digital

host using the SCK falling edge allows a faster reading rate,

provided it has an acceptable hold time. After the 20th SCK

falling edge or when CNV goes high (whichever occurs first),

SDO returns to high impedance.

AD4020

SDI

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

VIO

Figure 51. CS Mode, 3-Wire Turbo Mode Connection Diagram (SDI High)

SDO

D19

D18

D17

tDIS

SCK

tSCK

tSCKL

tSCKH

HSDO

tDSDO

CNV

ACQUISITION

tCYC

ACQUISITION

CONVERSION

SDI = 1

tACQ

tEN

tQUIET1

tQUIET2

tCONV

Figure 52. CS Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (SDI High)

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