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Data Sheet

AD4020

Rev. A | Page 31 of 36

CS MODE, 4-WIRE TURBO MODE

This mode is typically used when a single AD4020 is connected

to an SPI-compatible digital host. It provides additional time

during the end of the ADC conversion process to clock out the

previous conversion result, giving a lower SCK rate. The AD4020

can achieve a throughput rate of 1.8 MSPS only when turbo

mode is enabled and using a minimum SCK rate of 71 MHz.

The connection diagram is shown in Figure 57, and the

corresponding timing diagram is shown in Figure 58.

This mode replaces the 4-wire with busy indicator mode by

programming the turbo mode bit, Bit 1 (see Table 14).

The previous conversion data is available to read after the CNV

rising edge. The user must wait tQUIET1 time after CNV is brought

high before bringing SDI low to clock out the previous conversion

result. The user must also wait tQUIET2 time after the last falling

edge of SCK to when CNV is brought high.

When the conversion is complete, the AD4020 enters the

acquisition phase and powers down. The ADC result can be

read by bringing its SDI input low, which consequently outputs

the MSB onto SDO. A pull-up resistor of 1 kΩ on the SDO line

is recommended. The remaining data bits are then clocked by

subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can capture the data, a digital

host using the SCK falling edge allows a faster reading rate,

provided it has an acceptable hold time. After the 20th SCK

falling edge or when SDI goes high (whichever occurs first),

SDO returns to high impedance.

AD4020

SDI

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

IRQ

VIO

1kΩ

CS1

Figure 57. CS Mode, 4-Wire Turbo Mode Connection Diagram

ACQUISITION

SDO

SCK

ACQUISITION

SDI

CNV

tSSDICNV

tHSDICNV

tCYC

tSCK

tSCKL

tEN

tHSDO

tDSDO

tDIS

tSCKH

D19

D18

D17

tQUIET1

tQUIET2

tACQ

CONVERSION

tCONV

Figure 58. CS Mode, 4-Wire Turbo Mode Timing Diagram

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