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Data Sheet

AD4020

Rev. A | Page 15 of 36

THEORY OF OPERATION

COMP

CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

262,144C

524,288C

LSB

SW+

MSB

LSB

SW–

MSB

262,144C

524,288C

IN+

REF

GND

IN–

Figure 29. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD4020 is a high speed, low power, single-supply, precise,

20-bit ADC based on a SAR architecture.

The AD4020 is capable of converting 1,800,000 samples per

second (1.8 MSPS) and powers down between conversions. When

operating at 10 kSPS, for example, it typically consumes 83 µW,

making it ideal for battery-powered applications because its

power scales linearly with throughput. The AD4020 has a valid

first conversion after being powered down for long periods.

The AD4020 provides the user with an on-chip track-and-hold

and does not exhibit any pipeline delay or latency, making it

ideal for multiplexed applications.

The AD4020 incorporates a multitude of unique ease of use

features that result in a lower system power and footprint.

The AD4020 has an internal voltage clamp that protects the

device from overvoltage damage on the analog inputs.

The analog input incorporates circuitry that reduces the nonlinear

charge kickback seen from a typical switched capacitor SAR input.

This reduction in kickback, combined with a longer acquisition

phase, means reduced settling requirements on the driving

amplifier. This combination allows the use of lower bandwidth

and lower power amplifiers as drivers. It has the additional benefit

of allowing a larger resistor value in the input RC filter and a

corresponding smaller capacitor, which results in a smaller RC load

for the amplifier, improving stability and power dissipation.

High-Z mode can be enabled via the SPI interface by programming

a register bit (see Table 14). When high-Z mode is enabled, the

ADC input has a low input charging current at low input signal

frequencies as well as improved distortion over a wide frequency

range up to 100 kHz. For frequencies above 100 kHz and

multiplexing, disable high-Z mode.

For single-supply applications, a span compression feature

creates additional headroom and footroom for the driving

amplifier to access the full range of the ADC.

The fast conversion time of the AD4020, along with turbo mode,

allows low clock rates to read back conversions even when running

at the full 1.8 MSPS throughput rate. Note that a throughput

rate of 1.8 MSPS can be achieved only with turbo mode enabled

and a minimum SCK rate of 71 MHz.

The AD4020 can be interfaced to any 1.8 V to 5 V digital logic

family. It is available in a 10-lead MSOP or a tiny 10-lead LFCSP

that allows space savings and flexible configurations.

The AD4020 is pin for pin compatible with some of the 14-/16-/

18-bit precision SAR ADCs listed in Table 8.

Table 8. MSOP and LFCSP 14-/16-/18-/20-Bit Precision SAR

ADCs

Bits

100 kSPS

250 kSPS

400 kSPS to

500 kSPS

≥1000 kSPS

201

Not applicable

AD40202

181

AD7989-12

AD76912

AD76902,

AD7989-52,

AD40112

AD40032,

AD40072,

AD79822,

AD79842

161

AD7684

AD7687

AD76882,

AD76932

AD40012,

AD40052,

AD79152

163

AD7680,

AD7683,

AD7988-12

AD7685,2

AD76942

AD76862,

AD7988-52

AD40002,

AD40042,

AD79802,

AD79832

143

AD7940

AD79422

AD79462

Not applicable

True differential.

Pin for pin compatible.

Pseudo differential.

CONVERTER OPERATION

The AD4020 is a SAR-based ADC using a charge redistribution

sampling digital-to-analog converter (DAC). Figure 29 shows

the simplified schematic of the ADC. The capacitive DAC consists

of two identical arrays of 20 binary weighted capacitors, which

are connected to the comparator inputs.

During the acquisition phase, terminals of the array tied to the

input of the comparator are connected to GND via the SW+ and

SW− switches. All independent switches connect the other

terminal of each capacitor to the analog inputs. Therefore, the

capacitor arrays are used as sampling capacitors and acquire the

analog signal on the IN+ and IN− inputs.

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