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AD4020

Data Sheet

Rev. A | Page 16 of 36

When the acquisition phase is complete and the CNV input

goes high, a conversion phase initiates. When the conversion

phase begins, SW+ and SW− opens first. The two capacitor

arrays are then disconnected from the inputs and connected to

the GND input. The differential voltage between the IN+ and

IN− inputs captured at the end of the acquisition phase is

applied to the comparator inputs, causing the comparator to

become unbalanced. By switching each element of the capacitor

array between GND and VREF, the comparator input varies by

binary weighted voltage steps (VREF/2, VREF/4, …, VREF/1,048,576).

The control logic toggles these switches, starting with the MSB,

to bring the comparator back into a balanced condition. After

the completion of this process, the control logic generates the

ADC output code and a busy signal indicator.

Because the AD4020 has an on-board conversion clock, the

serial clock, SCK, is not required for the conversion process.

TRANSFER FUNCTIONS

The ideal transfer characteristics for the AD4020 are shown in

Figure 30 and Table 9.

100...000

100...001

100...010

011...101

011...110

011...111

ANALOG INPUT

+FSR – 1.5 LSB

+FSR – 1 LSB

–FSR + 1 LSB

–FSR

–FSR + 0.5 LSB

Figure 30. ADC Ideal Transfer Function (FSR Is Full-Scale Range)

Table 9. Output Codes and Ideal Input Voltages

Description

Analog Input, VREF = 5 V

VREF = 5 V with Span Compression Enabled

Digital Output Code (Hex)

FSR − 1 LSB

+4.99999046 V

+3.99999237 V

0x7FFFF1

Midscale + 1 LSB

+9.54 µV

+7.63 µV

0x00001

Midscale

0 V

0x00000

Midscale − 1 LSB

−9.54 µV

−7.63 µV

0xFFFFF

−FSR + 1 LSB

−4.99999046 V

−3.99999237 V

0x80001

−FSR

−5 V

−4 V

0x800002

This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF).

This output code is also the code for an underranged analog input (VIN+ − VIN− below −VREF).

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