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AD9655

Data Sheet

MEMORY MAP REGISTER DESCRIPTIONS

For general information about the functions controlled in

Interfacing to High Speed ADCs via SPI.

Device Index (Register 0x05)

There are certain features in the map that can be set indepen-

dently for each channel, whereas other features apply globally

to all channels (depending on context), regardless of which

channel is selected. Bits[1:0] in Register 0x05 can be used to

select which individual data channel is affected by the next SPI

action. The output clock channels can be selected in Register 0x05,

as well. A smaller subset of the independent feature list can be

applied to those devices.

Refer to the following sequence of SPI writes for an example of

how to use Register 0x5 to power down Channel B while keeping

Channel A active:

1. SPI_Write (0x05, 0x02)—designates Channel B to be

affected by the next local SPI register instruction.

2. SPI_Write (0x22, 0x01)—powers down the Channel

previously designated.

3. SPI_Write (0x05, 0x31)—designates DCO, FCO and

Channel A to be affected by future local SPI register

instruction (optional).

4. SPI_Write (0x08, 0x03)—digital reset.

5. SPI_Write (0x08, 0x00)—takes the device back to

normal operation.

Power Modes (Register 0x08)

Bits[7:2]—Open

Bits[1:0]—Power Mode

In normal operation (Bits[1:0] = 00), both ADC channels are

active.

In power-down mode (Bits[1:0] = 01), the digital datapath clocks

are disabled while the digital datapath is reset. Outputs are disabled.

In standby mode (Bits[1:0] = 10), the digital datapath clocks

and the outputs are disabled. Do not invoke standby mode

while foreground calibration is in progress. Foreground

calibration is invoked automatically at power-up and by

executing a digital reset with Register 0x08. Foreground

calibration completion is indicated by the contents of

During a digital reset (Bits[1:0] = 11), a foreground calibration is

invoked, all the digital datapath clocks and the outputs (where

applicable) on the chip are reset, except the SPI port. Note that the

SPI is always left under control of the user; that is, it is never

automatically disabled or in reset (except by power-on reset).

Enhancement Control (Register 0x0C)

Bits[7:3]—Open

Bit 2—Chop Mode

For applications sensitive to offset voltages and other low

frequency noise, such as homodyne or direct conversion

receivers, chopping in the first stage of the AD9655 is an

available feature, enabled by setting Bit 2. In the frequency

domain, chopping translates offsets and other low frequency

noise to fCLK/2, where it can be filtered.

Bits[1:0]—Open

Output Mode (Register 0x14)

Bit 7—0

Bit 6—LVDS-ANSI/LVDS-IEEE Option

Setting this bit selects the LVDS-IEEE (reduced range) option.

The default setting is LVDS-ANSI. When LVDS-ANSI or the

LVDS-IEEE reduced range link is selected, the driver current is

automatically selected to give the proper output swing.

Table 19. LVDS-ANSI/LVDS-IEEE Options

Output

Mode, Bit 6

Output Mode

Output Driver Current

LVDS-ANSI

Automatically selected to

give proper swing

LVDS-IEEE reduced

range link

Automatically selected to

give proper swing

Bits[5:3]—000

Bit 2—Output Invert

Setting this bit inverts the output bit stream.

Bit 1—Open

Bit 0—Output Format

By default, this bit is set to send the data output in twos

complement format. Clearing this bit to 0 changes the output

mode to offset binary.

Rev. 0 | Page 34 of 37

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